Part Number: LMH1983
Please advise me on my question bellow.
Can you explain how LMH1983 behaves when it is set into
(1) 00, Always drift lock,
(2) 01, Drift Lock if
(3) 1x, Always Crash Lock
I suppose that in (1)00, “Always Drift lock mode”, LMH1983 smoothly shifts
TOF1 timing and try to align to the input frame regardless input and
output video timing difference.
In (2)01, “Drift lock if” mode, LMH1983 smoothly shifts TOF1 timing and try
to align to the input frame, as long as, input and output video timing
difference is less than two video lines, otherwise, it makes Cras lock.
In (3) 1x, “Always Crash Lock mode”, LMH1983 makes Crash lock,
regardless input and output video timing difference.
In the meantime, the datasheet express (on Page 28, as shown below)
Question: Please let me know which reflects the proper behavior of the LMH1983.
This bit sets the PLL1/TOF1 output synchronization behavior
when the same reference is reapplied following a momentary
LOR condition and TOF1 is within 2 lines of the expected location.
00 = Always Drift Lock – ensures the outputs drift smoothly back
to frame alignment without excessive output phase disturbances
01 = Drift Lock if output < (2LOA_window x 27 MHz Clock). Crash Lock
1X = Always Crash Lock – achieves the fastest frame alignment through
PLL/TOF counter resets, which can result in output phase disturbances
I'm not sure I understand the question, crash lock will result in the fastest syncing but also largest phase disturbance on the output. Whereas drift lock will smooth out the transition but just take longer. The in between condition is to provide a level at which to perform drift lock for a given LOR and back signal availability vs crash lock, so it's allows the potential to do either depending on what's better for the system.
Thanks and regards,
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In reply to Amin Eshraghi:
Thank you for your feedback.
The description of the datasheet is still strange to me
Can you make it cleared my question bellow?
The datasheet stats as bellow on page 28.
0x11 Alignment Control – TOF1 3:2 TOF1_Sync
01 = Drift Lock if output < (2LOA_window x 27 MHz Clock). Crash
The condition “< (2LOA_window x 27 MHz Clock)” means the No loss of align.
I suspect that it should be “ TOF1 is within 2 lines of the expected location”.
Please check it with design document.
In reply to user4779049:
I think I understand the question now. If loss of alignment is never reported then it wouldn't align (whether crash or drift), and from the given condition for drift lock it seems loss of alignment wouldn't be reported. Let me look into this and come back to you.
Thank you for understanding my question and am looking forward your feedback.
I am looking forward get the answer.
Register 0x15 is only taken into consideration when register 0x11 bits [3:2] are set to 01. When this condition is met the value programmed into 0x15 determines when loss of alignment occurs. After loss of alignment is determined, and the reference clock is reapplied, the TOF1 phase determines whether the device uses drift lock or crash lock mode to relock.
In reply to Vibhu Vanjari:
Let me get back to the original my question.
How dose LMH1983 act when it is set into the following three modes.
through address 0x11 bit 3:2.
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