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Part Number: LMK05318
I have a primary and redundant GPS receiver producing a 1-PPS output which I am planning to feed into the inputs of the LMK05318 and assign the primary with a higher priority and set the device to Auto-Revertive.
My question is after a period of time where neither of the inputs are valid (holdover) and an input becomes valid, will the 1-PPS output gradually bring itself inline with the valid input or will it "snap" to the input signal immediately? Do I also have to use hitless switching for this? If not I will use the ZDM functionality.
When hitless switching is enabled, the output phase will never come back and align with input phase. Instead, it will remain undisturbed when the reference is gone, and when the reference comes back. This is hitless switching with zero phase hit. If the phase relationship between input 1pps and output 1pps matters, then you can use ZDM.
By the way, please use LMK05318B instead, where 1pps input stability is improved.
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In reply to Hao Z:
Thank you for clarifying my understanding of what hitless switching actually means. For our application the phase relationship is paramount so it seems this is not appropriate for us.
When using the LMK05318B with 1-PPS input and output in ZDM, what is the behaviour when a 1-PPS input is lost then after a period of time is regained? Does the output snap to the input phase as soon as the input becomes valid or can the DPLL support a gradual shift back into phase?
Can you also recommend if there are any other chips which are more suited to having two 1-PPS inputs with automatic switchover and output synchronization with holdover capabilities for 1-PPS and ZDM in your range?
In reply to Matt Child:
The auto switchover and digital holdover are always available regardless of 1pps or not. With ZDM however, you'll need to issue a soft reset (toggle the soft_reset bit) to regain the phase relationship after switchover. Either way, I don't think the DPLL supports a gradual shift back in phase. There is phase slew control, though, in the new device LMK5C33216 which is still in the sampling stage. Whether or not the phase slew feature is available in ZDM I'll have to check with the development team.
A further question to the above topic: What is the behaviour when not operating in ZDM or Hitless modes when a 1PPS input becomes valid? If not using fastlock will the transition back to the input phase be more gradual?
For context, our application is to be able to automatically select one of two 1PPS inputs, sync a clock to the input and produce a 1PPS output. When neither of these inputs is valid we want to enter the holdover mode. When automatically exiting the holdover mode, it is important that there is a reasonably smooth transition to becoming realigned with a valid input, with the shift back to realignment being gradual.
Closing the duplicated question.
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