Part Number: CDCE6214
Customer is going to use CDCE6214 from 10Mhz to 54Mhz and wondering if using OXCO as reference clock, can it possibly make jitter <1ps?
DS mentioned with fractional mode, LVCMOS output can have typical 2ps.
I have assigned this to the responsibly party. In the meantime can you let us know if you're interested for LVCMOS only or differential output as well?
Thanks and regards,
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In reply to Amin Eshraghi:
In reply to Allan Fan:
If the datasheet says so then it's unlikely 1ps can be achieved. Performance-wise it needs to be LMK03318 or above.
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In reply to Hao Z:
Thanks for your reply. Would you please explain again in word why using good jitter OCXO compare to XO, the output jitter from clock generator is not good? or is any documents can share with us?
For a regular PLL, the phase noise transfer function from input to the output can be though of as a low pass filter, with the 3-dB bandwidth approximately equal to the loop bandwidth. Typical loop bandwidth for a clock gen (without jitter cleaning) can be 100kHz to 400kHz. Therefore, the phase noise at below 100kHz goes directly from the input to the output.
If you find an OCXO and an XO and compare their phase noise performance between 12kHz and 100kHz, you'll see that typically an OCXO has worse phase noise than an XO.
OCXO is much better than XO in terms of frequency accuracy and close-in phase noise (<100Hz).
Would you please provide phase noise data for 10Mhz to 54Mhz with 0.1K, 1K, 10K, 100K, 1M, 10M offset for customer reference?
Which device are we talking about? This will take at least a week considering the availability of phase noise analyzer and lab access during COVID situation. Please also send me the required phase noise mask if there is any. Normally if we have a lot of margin there's no need for measurement.
Customer is considering CDCE6214. Here is the target criteria. Please help evaluate if it can meet customer's need. Thanks.
If I understand correctly, you want to see the performance of the CDCE6214 with 10MHz reference and 54MHz output frequency, correct? Actually the desired mask can be mostly achieved with integer mode (N=243, PSA=5, CHDIV=9, no attempt made to optimize loop filter settings):
In addition, since you mentioned the fractional divider, do you know if the customer requires the fractional divider enabled (for example, for DCO mode or SSC)? In fractional mode the phase detector frequency can be increased by a factor of 2 which seems to benefit the phase noise more than any penalty for using the fractional divider (N=121, NUM=5, DEN=10, first order fractional, PSA=5, CHDIV=9, no attempt made to optimize loop filter settings):
However, there will be larger spurious contributions if the N-divider denominator must be made large for fine-tuning in DCO mode or other similar effects (N=121, NUM=5000000, DEN=10000000, first order fractional, PSA=5, CHDIV=9, no attempt made to optimize loop filter settings):
In reply to Derek Payne:
This is Alpha HW engineer Adis,
I can't understand how using integer mode to get 54MHz output from 10MHz reference input, so i mentioned the fractional divider at the beginning.
If as you said integer mode can work. it is great !
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