CDCE6214: Jitter performance with OXCO

Hi Allan,

If the datasheet says so then it's unlikely 1ps can be achieved. Performance-wise it needs to be LMK03318 or above.

Regards,
Hao

Hi Allan,

For a regular PLL, the phase noise transfer function from input to the output can be though of as a low pass filter, with the 3-dB bandwidth approximately equal to the loop bandwidth. Typical loop bandwidth for a clock gen (without jitter cleaning) can be 100kHz to 400kHz. Therefore, the phase noise at below 100kHz goes directly from the input to the output.

If you find an OCXO and an XO and compare their phase noise performance between 12kHz and 100kHz, you'll see that typically an OCXO has worse phase noise than an XO.

OCXO is much better than XO in terms of frequency accuracy and close-in phase noise (<100Hz).

Regards,
Hao

Hi Allan,

If I understand correctly, you want to see the performance of the CDCE6214 with 10MHz reference and 54MHz output frequency, correct? Actually the desired mask can be mostly achieved with integer mode (N=243, PSA=5, CHDIV=9, no attempt made to optimize loop filter settings):

In addition, since you mentioned the fractional divider, do you know if the customer requires the fractional divider enabled (for example, for DCO mode or SSC)? In fractional mode the phase detector frequency can be increased by a factor of 2 which seems to benefit the phase noise more than any penalty for using the fractional divider (N=121, NUM=5, DEN=10, first order fractional, PSA=5, CHDIV=9, no attempt made to optimize loop filter settings):

However, there will be larger spurious contributions if the N-divider denominator must be made large for fine-tuning in DCO mode or other similar effects (N=121, NUM=5000000, DEN=10000000, first order fractional, PSA=5, CHDIV=9, no attempt made to optimize loop filter settings):

Regards,

Hi Adis,

I attached the TICS Pro integer-mode configuration I used below.

CDCE6214_10MHz_54MHz_Integer.tcs

Regards,