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LMK04828: CLKIN0 used in single end mode with resistor divider

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Replies: 5

Views: 81

Part Number: LMK04828

Hi, Team

My customer is using LMK04828, they found sometimes get unlock issue, then they increased the CLKin amplitude from 800mV to 900mV by adjust a resistor divider. Then they fount it is better, and solve the issue.

May I know if the 150Ohm + 330Ohm resistor divider is allowed  for the input configuration?

Any explanation for the optimization?

Analog FAE from Shenzhen, China

  • Hello Harson,

    The recommended input configurations for a single-ended termination on the LMK04828 are as followed:

    The resistor divider of 150 ohm + 330 ohm will work as well, but you will obtain better performance if the above configurations are used.

    The reason for the optimization is because the larger input signal results in a larger range for the PLL to lock to.

    Regards,

    Kia Rahbar

  • In reply to Kia Rahbar:

    I use CLKin0 input as reference clock source,single ended,AC coupled.CLKinx_TYPE is set to bipolar buffer mode. The Vpp of the clock is 0.9V, the PLL is loss of lock. When I change the CLKinx_TYPE to MOS buffer mode, the PLL is locked.

     If the CLKinx_TYPE is MOS buffer mode and the clock source Vpp is about 0.8V, the PLL is loss of lock.

    The input range is 0.35Vpp ~ 2.4Vpp. Why is PLL out of lock when VPP is 0.8V?

  • In reply to user6193156:

    Hello,

    The cause of the issue may be due to the resistor divider causing reflections at the input. Instead of the divider, can you try using a 50 ohm resistor pulled down to ground as shown below? Please let me know if this locks the PLL.

    Regards,

    Kia Rahbar

  • In reply to Kia Rahbar:

    When I use 50 ohm pulled down resistor, the clock Vpp is 440mV, the PLL is loss of lock. When I increase Vpp to 620mV, PLL is lock.But in the test yesterday,the PLL out of lock when VPP is 800mV.

    When I use 500 ohm pulled down resistor,the Vpp is 990mV, the PLL is lock.

    The clock source is 10MHz sine wave.

  • In reply to user6193156:

    Hello,

    When your clock Vpp is 440mV with a 50 ohm pull down resistor, the PLL is loss of lock because the signal is too small. 440mV is very close to the 0.35 Vpp threshold, so it is difficult for the PLL to lock to this signal.

    As I stated in my previous post, the 800mV case is not locking due to the reflections at the input.

    Please use the 50 ohm pull down resistor with a larger Vpp (such as the 620mV case). You will obtain no reflections with the 50 ohm pull down, thus leading to the best performance.

    Regards,

    Kia Rahbar