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LMK04828 Un-lock Status Indicate Issue

Other Parts Discussed in Thread: LMK04828, LMK00304

Hi Team,

 

Currently my customer finds that the LMK04828 fail to indicate the un-lock status. Can you help to check the reason? Thank you.

They are only using the PLL2. The LMK04828’s OSCin is from LMK00304 output. When we disable LMK00304 output, the LMK04828 should indicate that the PLL is unlocked. But sometimes the LMK04828 doesn’t indicate the un-lock status. In this case, we tried two ways to let the LMK04828 to indicate the unlock status:

1. we use a oscilloscope to probe the LMK04828’s OSCin’s pin, the device indicates the unlock status.

2. The device’s reg 0x140 is set to 0x80 before. Set the 0x140=0x90 manually -> some LMK04828 indicates the un-lock status -> Read back the 0x140 register 0 -> Some devices indicate the un-lock status, and some don’t.

Seems that the un-lock indicate needs some trigger action to act normally. Can you help to give some advice?

 

 

 

  • Hello, 

    The response for this will take a few days as all of US is on thanksgiving holidays. Expect an answer by next week. 

    Thanks and regards,

    Amin

  • Hello Qiang,

    PLL2's lock status is determined by the Status_LD2 pin. By default the Status_LD2 pin is configured as high (shown below).

    In order for the Status_LD2 to present the correct status, it must be programmed by the PLL2_LD_MUX. The mux values below set the output value of the Status_LD2.

    If the PLL2_LD_MUX is set to the correct value, then the Status_LD2 will reflect the correct locking status.

    Regards,

    Kia Rahbar

  • Kia,

    Thank you for response even on Thanksgiving day. We have checked the 0x16E reg to be 0x13, which means that the bit[3-7] is 0x2, it's MUXed to PLL2DLD. So maybe the MUX configuration isn't the root cause. Do we have any other trigger needed to indicate the unlock status?

    Thank you.

     

  • Hello Qiang,

    The PLL2_DLD_CNT register also affects locking status. If the user-specified PLL2_DLD_CNT value is small, then the lock detect will be asserted for a larger window.

    Please reference section 9.3.6 (shown below) in the LMK04828 data sheet for a further description on the digital lock detect.

    Table 73 in the LMK04828 data sheet shows the values that PLL2_DLD_CNT can be set to.

    Regards,

    Kia Rahbar

  • Kia,

    The 0x16A is 0x20 and 0x16B is 0x0. We have tried to sweep the PLL2_DLD_CNT value from 0x1 to 0x3FFF, but the issue still there. Seems that the PLL2_DLD_CNT only influence the time to lock detect, but not if to lock detect.

  • Hello Qiang,

    The Status_LD2 register and the RB_PLL2_LD both monitor PLL2 lock detect. Do both indicate lock when it should be unlocked?

    Regards,

    Kia Rahbar

  • Kia,

    Yes, they both indicate lock when it should be unlocked.

  • Hello Qiang,

    The reason the PLL fails to indicate unlock is because the state machine that indicates unlock gets stopped when there is no OSCin. When OSCin is interrupted, there is no clock to run the state machine shown below. 

    Since the state machine is stopped, the locking status remains locked (leading to the problem you are encountering).

    Regards,

    Kia Rahbar

  • Kia,

    Based on the state machine working model, there is no way to let the device indicate the unlock status when there is no OSCin. I'm I right? But it can't explain why when we probe the OSCin pin by oscilloscope the device indicate the unlock status..

    Thank you.

  • Hello Qiang,

    That is correct. The reason the device indicates unlock when you probe the OSCin pin could be due to the noise from the oscilloscope acting as a clock for the state machine.

    Regards,

    Kia Rahbar

  • Kia,

    Is there any register to indicate the state machine's state? I'm asking this to check if we can judge that the state machine has stopped.

    Also, is there any other way to let the device indicate the un-lock status when there is no OSCin?

    Thanks!

  • Hello Qiang,

    The Status_LD2 register monitors the digital lock detect signal, but there is no register to indicate whether the state machine is operating. You will have to conclude that the state machine is stopped when there is no OSCin in single PLL mode.

    The device will always be unlocked if there is no OSCin. An input signal is required for the PLL to lock. The indicator does not effect device functionality. As long as you know the device is unlocked when there is no OSCin, then it does not matter whether the indicator is high or low.

    Regards,

    Kia Rahbar

  • Hi Kia,

    My customer can't know whether the OSCin signal is lost or not, so they can't know whether the PLL lock status machine works fine. Do we have the reg to read if the OSCin signal is detected by LMK04828? And if no, do we have the plan to let the status machine work normally when OSCin lost?

    Thank you!

  • Hello Qiang,

    To determine if the OSCin signal is detect, you can check the OSCout pin. If the OSCout pin has a signal, then the OSCin pin has a signal.

    Since OSCin is our only input, the state machine will not work normally if OSCin is lost. You will have to assume the PLL is unlocked if there is no OSCout signal.

    Regards,

    Kia Rahbar