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LMK04826: Zero Delay Mode Configuration -- Multi LMK Synchronization

Part Number: LMK04826

Hi 


In my custom Board, I am trying to Synchronize 3 LMKs (LMK04826) devices with respect to input clock of 100 MHz.

I am doing Following Configurations

1. LMK 1 in Zero Delay Mode -- Sysref as Feedback.

2. Toggle Sync pin of LMK 1.

3. LMK 2 in Zero Delay Mode -- Sysref as Feedback.

4. Toggle Sync pin of LMK 2.

5. LMK 3 in Zero Delay Mode -- Sysref as Feedback.

6. Toggle Sync pin of LMK 3.

1. But Outputs of all LMK's are not alligned. I have attached my configurations. Please check my configurations.

2. In Zero Delay mode, Is it required to toggle SYNC pin to reset the dividers ??? or they will be resetted at rising edge of Feedback clock ?? 

3. In Zero Delay Mode, Feedback frequency = GCD(all outputs, input) or Lowest Frequency ??. GCD is not always the lowest Frequency

4. In Zero Delay Mode, Is it Required to maintain R divider as 1 ?? (Is it required to maintain OSC in Frequency same as PLL 2 PDF Frequency??)

LMK_1_NCO_1_2_100.txt
R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x00055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x010002
R257	0x010155
R258	0x010255
R259	0x010301
R260	0x010422
R261	0x010500
R262	0x0106F0
R263	0x010755
R264	0x010802
R265	0x010955
R266	0x010A55
R267	0x010B01
R268	0x010C22
R269	0x010D00
R270	0x010EF0
R271	0x010F55
R272	0x011002
R273	0x011155
R274	0x011255
R275	0x011301
R276	0x011422
R277	0x011500
R278	0x0116F0
R279	0x011755
R280	0x011819
R281	0x011955
R282	0x011A55
R283	0x011B01
R284	0x011C22
R285	0x011D00
R286	0x011EF0
R287	0x011F11
R288	0x012019
R289	0x012155
R290	0x012255
R291	0x012301
R292	0x012422
R293	0x012500
R294	0x0126F0
R295	0x012711
R296	0x012819
R297	0x012955
R298	0x012A55
R299	0x012B01
R300	0x012C22
R301	0x012D00
R302	0x012EF0
R303	0x012F11
R304	0x013019
R305	0x013155
R306	0x013255
R307	0x013301
R308	0x013402
R309	0x013500
R310	0x0136F1
R311	0x013701
R312	0x013820
R313	0x013903
R314	0x013A00
R315	0x013B19
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013F15
R320	0x01408B
R321	0x014100
R322	0x014200
R323	0x014311
R324	0x0144FF
R325	0x01457F
R326	0x014618
R327	0x01471A
R328	0x014802
R329	0x014942
R330	0x014A02
R331	0x014B16
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015003
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015678
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A78
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0B
R352	0x016000
R353	0x016101
R354	0x0162A4
R355	0x016300
R356	0x016400
R357	0x016505
R369	0x0171AA
R370	0x017202
R380	0x017C18
R381	0x017D77
R358	0x016600
R359	0x016700
R360	0x016801
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017300
R386	0x018200
R387	0x018300
R388	0x018400
R389	0x018500
R392	0x018800
R393	0x018900
R394	0x018A00
R395	0x018B00
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53

LMK_2_NCO_1_2_100.txt
R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x00055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x010002
R257	0x010155
R258	0x010255
R259	0x010301
R260	0x010422
R261	0x010500
R262	0x0106F0
R263	0x010755
R264	0x010802
R265	0x010955
R266	0x010A55
R267	0x010B01
R268	0x010C22
R269	0x010D00
R270	0x010EF0
R271	0x010F55
R272	0x011019
R273	0x011155
R274	0x011255
R275	0x011301
R276	0x011422
R277	0x011500
R278	0x0116F0
R279	0x011711
R280	0x011819
R281	0x011955
R282	0x011A55
R283	0x011B01
R284	0x011C22
R285	0x011D00
R286	0x011EF0
R287	0x011F11
R288	0x012001
R289	0x012155
R290	0x012255
R291	0x012301
R292	0x012422
R293	0x012500
R294	0x0126F9
R295	0x012701
R296	0x012801
R297	0x012955
R298	0x012A55
R299	0x012B01
R300	0x012C22
R301	0x012D00
R302	0x012EF8
R303	0x012F00
R304	0x013019
R305	0x013155
R306	0x013255
R307	0x013301
R308	0x013402
R309	0x013500
R310	0x0136F9
R311	0x013700
R312	0x013820
R313	0x013903
R314	0x013A00
R315	0x013B19
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013F15
R320	0x01408B
R321	0x014100
R322	0x014200
R323	0x014311
R324	0x0144FF
R325	0x01457F
R326	0x014618
R327	0x01471A
R328	0x014802
R329	0x014942
R330	0x014A02
R331	0x014B16
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015003
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015678
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A78
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0B
R352	0x016000
R353	0x016101
R354	0x0162A4
R355	0x016300
R356	0x016400
R357	0x016505
R369	0x0171AA
R370	0x017202
R380	0x017C18
R381	0x017D77
R358	0x016600
R359	0x016700
R360	0x016801
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017300
R386	0x018200
R387	0x018300
R388	0x018400
R389	0x018500
R392	0x018800
R393	0x018900
R394	0x018A00
R395	0x018B00
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53

 

LMK_3_NCO_1_2_100.txt
R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x00055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x010002
R257	0x010155
R258	0x010255
R259	0x010301
R260	0x010422
R261	0x010500
R262	0x0106F0
R263	0x010755
R264	0x010802
R265	0x010955
R266	0x010A55
R267	0x010B01
R268	0x010C22
R269	0x010D00
R270	0x010EF0
R271	0x010F55
R272	0x011002
R273	0x011155
R274	0x011255
R275	0x011301
R276	0x011422
R277	0x011500
R278	0x0116F0
R279	0x011755
R280	0x011819
R281	0x011955
R282	0x011A55
R283	0x011B01
R284	0x011C22
R285	0x011D00
R286	0x011EF0
R287	0x011F11
R288	0x012019
R289	0x012155
R290	0x012255
R291	0x012301
R292	0x012422
R293	0x012500
R294	0x0126F0
R295	0x012711
R296	0x012819
R297	0x012955
R298	0x012A55
R299	0x012B01
R300	0x012C22
R301	0x012D00
R302	0x012EF0
R303	0x012F11
R304	0x013019
R305	0x013155
R306	0x013255
R307	0x013301
R308	0x013402
R309	0x013500
R310	0x0136F9
R311	0x013700
R312	0x013820
R313	0x013903
R314	0x013A00
R315	0x013B19
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013F15
R320	0x01408B
R321	0x014100
R322	0x014200
R323	0x014311
R324	0x0144FF
R325	0x01457F
R326	0x014618
R327	0x01471A
R328	0x014802
R329	0x014942
R330	0x014A02
R331	0x014B16
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015003
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015678
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A78
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0B
R352	0x016000
R353	0x016101
R354	0x0162A4
R355	0x016300
R356	0x016400
R357	0x016505
R369	0x0171AA
R370	0x017202
R380	0x017C18
R381	0x017D77
R358	0x016600
R359	0x016700
R360	0x016801
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017300
R386	0x018200
R387	0x018300
R388	0x018400
R389	0x018500
R392	0x018800
R393	0x018900
R394	0x018A00
R395	0x018B00
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53

  • Hello, 

    The response for this will take a few days as all of US is on Thanksgiving holidays. Expect an answer by next week. 

    Thanks and regards,

    Amin

  • Hello Pavan,

    1. None of your configurations enable the digital delays. I think since you are using SYSREF as the zero-delay feedback, the SYSREF digital delay does not need to be enabled, so that should be okay. But the clock outputs need to have the delays enabled and the _CNTH and _CNTL values programmed correctly so that they can be aligned to the SYSREF. Note that the digital delays only need to be active during a divider reset; after the divider reset, they can be powered down again to save current.

    2. Yes, the output dividers do need to be reset. The SYSREF divider does not need to be reset, since it is the zero-delay source. But the clock output dividers do need to be reset. You mentioned toggling the SYNC pin, but because of the way you've configured the devices, no synchronization will happen unless you make changes to the SYNC_DISx bits and the SYSREF_MUX during the SYNC procedure. If you set SYNC_DISx bits to 0 while the continuous SYSREF is selected, the clock outputs will be in reset for 50% of the SYSREF period at all times. So your synchronization procedure would instead look like:
        a) Change SYSREF_MUX to reclocked (0x1)
        b) Set all required SYNC_DISx bits = 0 (you can skip SYNC_DISSYSREF since the SYSREF divider is in the zero-delay feedback path)
        c) Toggle the SYNC pin for at least 10ns. The clock output dividers will be synchronized to the SYSREF divider edge.
        d) Restore the SYNC_DISx bits = 1
        e) Restore SYSREF_MUX = continuous mode
        f) Repeat the process on each downstream PLL after lock is reacquired
    You will need to select the digital delay values that align the clock to the SYSREF properly, and the digital delays for each used clock output will need to be active while the dividers are reset. After the dividers are reset, you can disable the digital delays again for power savings.

    3. For a single deterministic phase, the feedback frequency should be GCD(inputs, outputs). I see that your feedback frequency is 100MHz. The 100MHz SYSREFs would always be in phase between each device, and the 100MHz device clocks would always be in phase between each device after synchronizing their dividers at any SYSREF edge, since they are integer multiples of the feedback frequency. But since your feedback frequency is 2x GCD frequency, there could be two different phases for the 1250MHz clock between each device. Fortunately it is not difficult to plan around potential two phase mismatch: you can split your 100MHz reference clock into "odd" and "even" cycles, and only ever toggle the SYNC pin on one or the other. This essentially guarantees that the divider reset only occurs at GCD(inputs, outputs), instead of 2xGCD.

    4. The short answer is no, R-divider does not need to be 1, and oscin does not need to be the same as the PLL2 Fpd. You could generate 100MHz and 200MHz outputs, with 100MHz input, using 50MHz phase detector frequency, in zero-delay mode, to produce a single consistent phase across many devices. When the phase detector frequency is an integer divide of the GCD frequency, it becomes possible for R/N to be > 1. What's more important is that the synchronization event is coordinated with the GCD frequency.

    The whole reason for setting up the SYSREF as the zero-delay feedback is because the SYSREF can be configured as GCD(inputs, outputs), and the SYNC pulse can be retimed to the GCD by a divider in the feedback loop, without needing to worry about any timing-critical synchronization. If your SYSREF frequency is not equal to your GCD(inputs, outputs), there could be more than one phase between different systems with the same frequencies, because there are SYSREF / GCD(inputs, outputs) different possible phases to which the SYNC pulse could be retimed. This isn't always a bad thing, either: in exchange for keeping track of the SYNC timing with respect to the GCD (by counting reference input cycles), the phase detector frequency can usually be increased, allowing for better PLL2 performance.

    Regards,