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Replies: 13
Views: 264
Part Number: LMK04828
Hello
Now I try to "direct sysref mode" but It doesnt work (no output and signal fixed to LOW . input SYNC signal is High.)
My Configuration is as below. (SYSREF signal is conected to Clkin0 )
0x143 0x10 SYNC_MODE
0x139 0x04 SYSREF_MUX,SYSREF CLKin0_MUX
0x147 0x18 CLKin0_OUT_MUX
0x104 0x20 SDCLKoutY_DDLY
0x140 0x07 SYSREF_DDLY_PD,PLSR,PD
0x106 0x30 SDCLKoutY_PD
0x107 0x55 SDCLKoutY_FMT
Would you please tell me something wrong point?
Takeshi
In reply to Timothy T:
Hello Timothy
Im so Sorry.when I changed bipolar ⇒ mos , I changed ClKin enable bit as 0 too.that was my mistake,So,It works in Schematic 2.
In schematic 1 it didnt work .Maybe the reason is input wave edge is not good by reflection.(there isnt figure in figure1, but I used 3 receive (fanout 3 LM04828×1 FPGA×2))
I changed input signal as CMOS and CLKin buffer type as mos then input wave was improved and it works.Sysref output signal frequency is no problem.
This circuit is tempolary ,so I will change LMK04803 to LMK04828 and SYSREF signal connect 1 on 1.
And by your suggestion, I want to optimaize value of AC coupling capacitor .
Do you have reccomend value?
In reply to user5983069:
Hello Takeshi-san,
Yes, please confirm using one LVDS output to one LVDS input. I expect it will work.
As for needing a larger value capacitor. I was examining my setup, the 0.1 uF is acceptable. I was originally testing using a balun to convert a single ended signal to differential for testing. The balun was causing my excessive droop, not the capacitors.
73,Timothy
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