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LMK04828: Forwarding CLKin0 to SDCLKoutY

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Replies: 10

Views: 110

Part Number: LMK04828

Hi,

i am planning to set the LMK04828 in nested ZDM mode + reclock clkin0 for sysref.

Below in my frequency plans:

Dclk = 250MHz

SDclk = 6.25MHz

Clkin1 = 250MHz

clkin0 = 6.25MHz

i set the internal SYSREF divider to output 250 MHz and use it as ZDM feedback for PLL1. To get the SDCLK, i wanted to configure the SYSREF muxes to forward CLKin0 to SDCLKoutY as the figure attached below. however, i am not able to do so in TICS. the source of SDCLKout is from either SYSREF divider or DCLK. 

Can you advise how to configure correctly? 

Thanks.

  • i attached the images again.

  • In reply to KGY:

    Hi KGY,

    On the SYNC/SYSREF page, set the following controls:

    • CLKin0_OUT_MUX = SYSREF_MUX
    • SYSREF_MUX = Re-clocked
    • SYSREF_CLKin0_MUX = From SYSREF_MUX
    • SYNC_DISx = 1 (prevents LMK04828 divider reset when a SYSREF pulse occurs)
    • SYNC_MODE = SYNC Pin Disabled

    Regards,

    Derek Payne

    Texas Instruments

  • In reply to Derek Payne:

    Hi Derek,

    Thanks for the prompt reply.

    after the settings on the "SYNC/SYSREF" page, what settings should i do on the "Clock Outputs" page to get the clkin0 forwarded to the SDCLKoutY?

    Thanks.

  • In reply to KGY:

    Hi KGY,

    Based on the image you provided, you already have SDCLKout1 configured correctly to distribute the re-clocked signal from CLKin0 (SDCLKoutY_MUX set to SYSREF, SDCLKoutY_PD=0). You can use this as a template for setting the other SDCLKoutY outputs.

    Regards,

    Derek Payne

    Texas Instruments

  • In reply to Derek Payne:

    Hi Derek,

    if my overall clock design is as attached and the slave is configured as above (ZDM with reclocked clkin0), does my design ensure that all the slave LMK04828s' outputs will be synchronized and have the rising edge at the same time?

  • In reply to KGY:

    Hi KGY,

    I ended up with a lot to say, but much of it is supplementary. My core answer is the three paragraphs below; the remainder are notes that are covered in the datasheet, but which are helpful to have summarized in one location.

    The design as drawn, with the configuration in your TICS Pro screenshots and description, should ensure that the SYSREF edge of each slave LMK is synchronous with the DCLK output of each master LMK. It looks like the master device is generating the 6.25MHz SYSREF, and since the reference of the master device is 25MHz I assume the zero-delay PLL1 feedback is the SYSREF and the phase detector rate is also 6.25MHz (or an integer divide of 6.25MHz).

    In practice, you will need to SYNC the dividers to ensure that every slave DCLK is aligned after programming, because programming the divider value effectively randomizes the divider phase. The timing and source of the SYNC are not critical for the master device. It is only important that all the master LMK DCLKs are aligned with each other and the SDCLKs are at least slightly delayed from the DCLK edges, by setting the appropriate digital delays before the SYNC procedure. For the slave devices, as long as the SYNC is retimed to the slave LMK SYSREF divider (which is in-phase with the master's DCLKs and therefore simultaneous across all slave LMKs), the SYNC timing and source are not critical. As long as the digital delay values on the slave devices are all the same, the phase of all slave devices should agree after synchronization.

    Since all devices are in nested zero delay mode, I think the easiest way to ensure all devices are synchronized is to set SYNC_PLL1_DLD on the SYNC/SYSREF page during programming, set SYNC_DISx = 0 for all DCLK dividers (SYNC_DISSYSREF=1 still), lock the devices, and then set SYNC_DISx = 1 again. As the master LMK locks, SYNC from PLL1_DLD will de-assert, and all the master DCLKs will be synchronized. Setting SYNC_DISx = 1 at the end ensures the DCLK dividers are not needlessly reset by the SYSREF divider. After the master locks, the 250MHz DCLKs will begin switching, and the slave devices will begin to lock. As the slave LMKs lock, SYNC from PLL1_DLD will de-assert, and the SYNC signal of all the slave DCLKs will be synchronized to the master LMK 250MHz edge through the SYSREF divider re-clock. Setting SYNC_DISx = 1 at the end ensures the slave DCLK dividers are not needlessly reset by the re-clocked CLKin0 signal. After each slave device is locked, its 250MHz DCLKs will begin to switch. After each device is locked, SYNC_PLL1_DLD can be set to 0 to prevent unwanted signals to the SYSREF_MUX in the event of a temporary loss-of-lock. Note that after synchronization, the synchronization of all devices can persist through any device temporarily losing and re-acquiring lock, because of the zero-delay and because GCD(inputs, outputs) is always equal to the feedback frequency.

    Additional notes that may be useful:

    • The SYSREF global delay (SYSREF_DDLY) is not useful when the SYNC event is re-timed to the SYSREF divider edge, so SYSREF_DDLY_PD=1 makes sense for all devices (SYNC_PLLx_DLD with SYSREF divider feedback is also technically a SYNC event re-timed to the SYSREF divider edge). The SYSREF divider of the slave LMK operates at 250MHz, 3000/250 = 12, and local SYSREF delay only provides between 1.5 and 11 steps. This likely provides enough adjustment range to ensure the SDCLKs are aligned to the DCLK falling edge, or at least within the required setup and hold window, without using the device clock digital delays.
    • If the device clock digital delays are not needed for any output clock (for example on the master LMK, where all DCLKs should presumably share an edge), they can all be powered down, even during SYNC. This just means no extra VCO cycles will be added to the duration of the divider reset.
    • The SYSREF local delays (SDCLKoutY_DDLY) need to be manually reset before use after every POR. On first programming, set SYSREF_CLR=1 to reset the local delay blocks. The easiest way to ensure that SYSREF local delays are cleared is probably to program the register containing SYSREF_CLR (R323) twice in a row: once with SYSREF_CLR = 1, once with SYSREF_CLR = 0. Since SYSREF_CLR only needs to be asserted for 15 VCO cycles, the time between programming two SPI registers is more than enough to guarantee the register is cleared. If the SYSREF local delays are set to Bypass, then SYSREF_CLR procedure is not required.
    • The SYNC and SYSREF share a path (the SYSREF distribution path), so SYNC events can generate output pulses on SDCLKs. If you want to ensure that the SDCLKs do not change state while the PLLs are locking and SYNC is happening, you could set SYSREF_GBL_PD=1 and set SDCLKoutY_DIS_MODE to one of the options that maintains a constant output state. Once the SYNC is complete (i.e. the devices are locked), you can set SYSREF_GBL_PD=0 and the SDCLKs will behave normally.
    • If for any reason you need to generate a SYNC through software (for example if you don't want to use SYNC_PLL1_DLD), just set SYNC_MODE = SYNC pin, and toggle SYNC_POL (as long as SYSREF_MUX is in Normal or Re-clocked mode; slave LMKs should only use re-clocked mode). If the master LMK SYSREF_MUX is in pulser mode and SYNC_MODE is set to SPI (pulser) or SYNC Pin (pulser), writing any value to R318 (SYSREF_PULSE_CNT) or toggling SYNC_POL respectively could also generate a software SYNC.
    • System architecture thought that might save some money: Do the slave devices need to be in nested zero-delay dual-loop mode if the reference and feedback frequencies are 250MHz? The extra cost makes sense if you are trying to avoid the additive phase noise of the master clock at the slave PLL2 (i.e. if the slave LMK PLL2 Fpd frequency is close to 125MHz, the best case with 250MHz OSCin). But if the PLL2 Fpd frequency of the master or the slave LMKs is much lower than 125MHz, or if the Fpd frequency of the slave LMKs is much lower than the Fpd frequency of the master LMK, there would be almost no additive phase noise penalty for using PLL2-only zero-delay mode, and all the synchronization benefits would still apply. The only change to my above instructions would be to use SYNC_PLL2_DLD for the slave devices instead of SYNC_PLL1_DLD. I see 250MHz OSCout frequency from buffered OSCin in one of your images, so if this is representative of the VCXO you will use for the slave devices, nested mode is probably the right call. But I also see 500MHz DCLK output, so I'm not sure if I can consider OSCout frequency in that image as representative of the frequency plan.

    Regards,

    Derek Payne

    Texas Instruments

  • In reply to Derek Payne:

    Hi Derek,

    Thanks for the great information. 

    I have a few more questions.

    1. i wanted to get the best jitter at the slave outputs, so i have designed the slave to be in nested zero-delay dual-loop too. will there be difference in jitter performance for the below 2 cases?

    nested zero-delay dual-loop for both master and slave:

    master FPD1 = 6.25MHz,  master FPD2 = 125MHz, slave FPD1 = 25MHz, slave FPD2 = 125MHz

    master in nested zero-delay dual-loop, slave in PLL2-only zero-delay mode:

    master FPD1 = 6.25MHz,  master FPD2 = 125MHz, slave FPD2 = 125MHz

    2. On the master LMK, for the synchronization, is the sequence below correct?

    a) set SYNC_DISSYSREF=0 to  enable synchronization of the dividers

    b) set SYSREF_MUX to normal and toggle SYNC_POL 

    c) set SYNC_DISSYSREF=1

    d) set SYSREF_MUX to continuous

    Thanks.

  • In reply to KGY:

    Hello KGY,

    1. I think you will see better performance with both devices in nested zero-delay dual-loop mode (your first option), because the frequency of PLL2 Fpd in both master and slave devices is similar. Slave devices in PLL2 only mode would not be a performance benefit, in-band noise would increase by around 3dBc/Hz.
    2. For the synchronization sequence, the SYSREF divider does not need to be reset and SYNC_DISSYSREF will not have an effect, because the SYSREF output is used as the zero-delay feedback which can only have one phase (determined by reference input). In the image, I see you are using SYNC_PLL1_DLD=1. The programming sequence for the master device would then be:
    1. Initially, program SYNC_PLL1_DLD=1, and SYNC_DIS0, SYNC_DIS2, ..., SYNC_DIS12=0 to enable reset.
    2. Wait for PLL1 to lock.
    3. When PLL1 locks, the output dividers will be released from synchronization simultaneously, ensuring every slave device sees the reference clock at the same phase.
    4. After PLL1 locks, program SYNC_DIS0, SYNC_DIS2, ..., SYNC_DIS12=1 to prevent SYSREF edges from triggering divider reset again.
    5. Set SYSREF_MUX to continuous.
    • If you want to manually SYNC the master dividers instead of using SYNC_PLL1_DLD, the procedure is as follows:
      1. Initially, set SYNC_DIS0, SYNC_DIS2, ..., SYNC_DIS12=0 to enable reset.
      2. Set SYNC_MUX to SYNC pin, and SYSREF_MUX to re-clocked (for phase consistency; could technically be normal, but SYSREF to device clock phase would be randomized)
      3. Toggle SYNC_POL 0->1->0
      4. Set SYNC_DIS0, SYNC_DIS2, ..., SYNC_DIS12=1 to prevent SYSREF edges from triggering divider reset again.
      5. Set SYSREF_MUX to continuous.

    Regards,

    Derek Payne

    Texas Instruments

  • In reply to Derek Payne:

    Hi Derek,

    Thanks, I have clearer understanding now.

    A last question, is the configuration and the programming sequence(mentioned above) the same if i switch to LMK04832?

  • In reply to KGY:

    Hi KGY,

    The register programming is somewhat different between LMK04828 and LMK04832. The two devices are p2p compatible, but they do not share identical functionality. A comprehensive overview of the register map and functional changes between the devices is attached.

    LMK04828 to LMK04832 Migration Guide.pdf

    Regards,

    Derek Payne

    Texas Instruments