Part Number: LMK04821
I'm trying to design a loop filter for my LMK04821 design. I'm using a 50MHz external oscillator and configuring PLL2 VCO frequency to be 2000MHz. Where does the Fout in the PLLatinum Sim translate the TICS Pro view? I'm not sure if PLLatinum Sim is telling me the frequency I want to push to the clock distribution is not possible, or if I'm not configuring it correctly to match my TICS Pro configuration.
In PLLatinum sim - you'll configure the VCO for 2000 MHz, then you'll set an output frequency, this will auto-calculate the divider between VCO and output. Or you could program the divider and it will update the output frequency.
In TICS Pro - the PLL2 VCO0 should be set for 2000 MHz. Then in the "Clock Outputs" page you can type the output frequency desired into any of the CLKout frequency boxes on the right hand side. This will set the divider. Note, if the divider is /1 (2000 MHz), you will also need to set clock output select mux to "Divider+DCC+HS". I don't think this is done automatically.
Is there a specific error/warning you're getting in PLLatinum sim that makes you think you are not pushing a valid frequency to output? Please note that VCO0 and VCO1 have different frequency ranges.
More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html
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In reply to Timothy T:
No there was no specific error just wanted to make sure I was interpreting correctly across the platforms. Thanks!
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