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LMX2485E: RF input sensibility for frecuencies < 600 MHz

Part Number: LMX2485E

Hi,

I am designing a synthetizer using this PLL LMX2485E with a VCO from Crystek with 3dBm +/- 3 dB as RF output power.

In the LMX2485E data sheet, minimum RF input is defined as -8 dBm for all the temperature conditions.

My questions is related to the RF level in the RF input of PLL for the worst case.

- Minimum RF output from VCO: +0 dBm.

- Minimum RF input PLL: -8 dBm.

A commom -6dB divisor is  used to spli the RF signal for PLL and the rest of RF blocks. Besides, an isolation between VCO and PLL is implemented to avoid spurs in the output of oscillator.

But if this topology is used, the RF level to the input of PLL does not meet the -8dBm requirement as indicated in the following figure:

With this schematic and VCO output=0 dBm, the RF power input in the PLL is about -10dBm (non-compliance with the specification minimum -8dBm)

Please, could you help us with this issue?

Isiolation can be reduced, but spurs will be increased.

I have simulated to try to match better the PLL impedance and this is improved.

Including this matching network, the level is increased.

But this topology is not very common, and we do not know if this could have other problems.

Which is your recomendation?

Thanks in advance.

Best Regards,

Pedro

  • Hi Pedro,

    your pictures did not get through, would you please resend them again? Use the Insert/Edit Media icon in the menu bar to add picture in e2e post.

  • Hi Noel,

    I write again the message using "Insert MEdia".

    ********

    Hi,

    I am designing a synthetizer using this PLL LMX2485E with a VCO from Crystek with 3dBm +/- 3 dB as RF output power.

    In the LMX2485E data sheet, minimum RF input is defined as -8 dBm for all the temperature conditions. (Freq_RF <500MHz)

    My questions is related to the RF level in the RF input of PLL for the worst case.

    - Minimum RF output from VCO: +0 dBm.

    - Minimum RF input PLL: -8 dBm.

    A commom -6dB divisor is  used to spli the RF signal for PLL and the rest of RF blocks. Besides, an isolation between VCO and PLL is implemented to avoid spurs in the output of oscillator.

    But if this topology is used, the RF level to the input of PLL does not meet the -8dBm requirement as indicated in the following figure:

    With this schematic and VCO output=0 dBm, the RF power input in the PLL is about -10dBm (non-compliance with the specification minimum -8dBm)

    Please, could you help us with this issue?

    Isiolation can be reduced, but spurs will be increased.

    I have simulated to try to match better the PLL impedance and this is improved.

    Including this matching network, the level is increased.

    But this topology is not very common, and we do not know if this could have other problems.

    Which is your recomendation?

    Thanks in advance.

    Best Regards,

    Pedro

  • Hi Noel,

    Please, could you indicate me if you can see the figures in my previous remark?

    Thanks in advance.

    Best Regards,

    Pedro

  • Hi Pedro,

    Sorry to keep you waiting, it took me some time to follow up the history, as you know, this is a rather old device.

    The -8dBm requirement applies to when Fin frequency is 50MHz. The sensitive vs Fin frequency is similar to Figure 2 and Figure 3 in the datasheet.

    So if you are interested in 400 - 500MHz range, the sensitive is around -30dBm.

  • Hi Noel,

    Thank you very much for your feedback.

    Yes, you are right, this is an old device.

    The frequency range for oscillator is from 350 to 450MHz and we use RF_P=0 (Preescaler=8)

    The figure indicates the parameter for RF_P=1 (Preescaler 16). Is this similar for RF_P=0 (Preescaler=8) ??

    I understand that these are typical values and the guaranteed values for all frequency range (50-500MHz) and all temperature range is the indicated one in the table:

    Which minimum value we can use as guaranteed for 350-450 MHz and all temperatures range with RF_P=0 (Preescaler=8) ? -20dBm???

    Thanks in advance.

    Best Regards,

    Pedro

  • Hi Pedro,

    The sensitivity at frequency below 2GHz will be similar between prescalar = 8 and 16. 

    The process that we used to build this device is well known for having very good consistence over PVT, so the typical value is very closed to the guarantee value. To add some margin, right, -20dBm is a reasonable assumption. 

  • Hi Noel,

    Thank you very much for your support.

    Best Regards,

    Pedro