Hi,
I am designing a synthetizer using this PLL LMX2485E with a VCO from Crystek with 3dBm +/- 3 dB as RF output power.
In the LMX2485E data sheet, minimum RF input is defined as -8 dBm for all the temperature conditions.
My questions is related to the RF level in the RF input of PLL for the worst case.
- Minimum RF output from VCO: +0 dBm.
- Minimum RF input PLL: -8 dBm.
A commom -6dB divisor is used to spli the RF signal for PLL and the rest of RF blocks. Besides, an isolation between VCO and PLL is implemented to avoid spurs in the output of oscillator.
But if this topology is used, the RF level to the input of PLL does not meet the -8dBm requirement as indicated in the following figure:
With this schematic and VCO output=0 dBm, the RF power input in the PLL is about -10dBm (non-compliance with the specification minimum -8dBm)
Please, could you help us with this issue?
Isiolation can be reduced, but spurs will be increased.
I have simulated to try to match better the PLL impedance and this is improved.
Including this matching network, the level is increased.
But this topology is not very common, and we do not know if this could have other problems.
Which is your recomendation?
Thanks in advance.
Best Regards,
Pedro