LMK04828: DClk and Sysref

Hello Naveen,

Naveen kumar A said:

What is the sequence of registers to be written in order to generate continuous sysref?

For continuous SYSREF, in general writing the SYNC_DIS fields = 1 to prevent SYSREF from synchronizing output dividers

Register 0x144 = 0xff

and then:

SYSREF_MUX = SYSREF Continuous is sufficient.

--- Here is a more thorough list:

# Register 0x144 details:
SYNC_DISSYSREF = 1
SYNC_DIS0 = 1
SYNC_DIS2 = 1
SYNC_DIS4 = 1
SYNC_DIS6 = 1
SYNC_DIS8 = 1
SYNC_DIS10 = 1
SYNC_DIS12 = 1

# Some other fields for programming
SYNC_EN = 1
SYSREF_PD = 0        # Power up JESD204B SYSREF (actually needs to be powered up during the SYNC dividers)
SYSREF_MUX = 3       # Continuous SYSREF mode.
SYSREF_CLKin0_MUX = 0  # Feed SYNC/SYSREF path from SYSREF_MUX
SYSREF_REQ_EN = 0    # No SYSREF REQ mode.
SYSREF_PLSR_PD = 1   # Don't need the pulser.
SYSREF_CLR = 0

Naveen kumar A said:

I am generating 156.25 MHz from DCLK2 and 19.53625 MHz from SDClk3 and the same is generated from DClk12 and SDClk13. Both Dclk and SDClk are in LVDS standard with AC coupling capacitors.

The JESD link between ADc and FPGA fails randomly. Some times Sync pin is always low and sometimes Sync pin toggles.

Can you please help in identifying reason for that?

I don't have enough information to assist here.  Is this in a continuous SYSREF mode?

  > Note in general you don't want to use continuous SYSREF.  Having SYSREF continuously running consumes power and creates risk of crosstalk.  However if you just turn on and then off for synchronization, that's ok.

Naveen kumar A said:

I want Dclk to be generated when I configure LMK04828 and Sysref to be generated after I configure ADC and JESD Receive core.

I would program the device for pulser mode, configure the device.  Then when you need to sync, request a sequence of SYSREF pulses.  I guess if you are AC coupled, this may not work for you... in which case I would setup the device for pulser, never give the pulses, but then toggle the SYSREF_MUX between pulser and continuous mode as required for turning on or off sysref.

  > Do you have any interest in DC coupled SYSREF to the ADC12DJ3200?

73,
Timothy

Hello Naveen,

Naveen kumar A said:

0x13900, 0x14391, 0x14400, 0x144FF, 0x14310, 0x13903, 0x1FFD00, 0x1FFE00, 0x1FFF53

This appears good to prevent the DCLK/SYSREF from turning on off at the SYSREF frequency as you've set 0x144FF -- sync disable to all dividers.

I notice you've set the SDCLKoutY_DDLY = Bypass.  I do not suggest that.  That is primarily for if you want to route CLKin0 to SDCLKoutY directly.  At least set to 2 cycles.  (0x10c22) for SDCLKout3.

Naveen kumar A said:

Kindly suggest sequence of registers to be written with value.

Hmm.  The registers you have appear as if they should do the job.  When you say the DCLK and SYSREF are turning on and off...  can you share a scope plot of this?

Naveen kumar A said:

Do you have any interest in DC coupled SYSREF to the ADC12DJ3200?

Yes.

So the requirement for DC coupling is to reduce the Vcm of the clock signal to an acceptable level for the receiver.  The LCPECL output mode has been designed to provide a relatively high swing with a relatively low Vcm.  It's not low enough Vcm for the ADC12DJ3200 at about 1.1 V.  However it allows you to then created a voltage divider using the emitter resistors which have been broken into Rs + Rb.  The LCPECL can be divided down from the 1.1 V Vcm to 0.5 V Vcm while still maintaining differential swing levels required.

73,.
Timothy