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LMK04828: DClk and Sysref

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Replies: 3

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Part Number: LMK04828

Hi all,

I am using ADC12DJ3200 ADC interfaced via JESD204B with FPGA.

What is the sequence of registers to be written in order to generate continuous sysref?

I am generating 156.25 MHz from DCLK2 and 19.53625 MHz from SDClk3 and the same is generated from DClk12 and SDClk13. Both Dclk and SDClk are in LVDS standard with AC coupling capacitors.

The JESD link between ADc and FPGA fails randomly. Some times Sync pin is always low and sometimes Sync pin toggles.

Can you please help in identifying reason for that?

Also, Kindly give setting for below case,

I want Dclk to be generated when I configure LMK04828 and Sysref to be generated after I configure ADC and JESD Receive core.

Regards,

Naveen.A

  • Hello Naveen,

    Naveen kumar A
    What is the sequence of registers to be written in order to generate continuous sysref?

    For continuous SYSREF, in general writing the SYNC_DIS fields = 1 to prevent SYSREF from synchronizing output dividers

    Register 0x144 = 0xff

    and then:

    SYSREF_MUX = SYSREF Continuous is sufficient.

    --- Here is a more thorough list:


    # Register 0x144 details:
    SYNC_DISSYSREF = 1
    SYNC_DIS0 = 1
    SYNC_DIS2 = 1
    SYNC_DIS4 = 1
    SYNC_DIS6 = 1
    SYNC_DIS8 = 1
    SYNC_DIS10 = 1
    SYNC_DIS12 = 1

    # Some other fields for programming
    SYNC_EN = 1
    SYSREF_PD = 0        # Power up JESD204B SYSREF (actually needs to be powered up during the SYNC dividers)
    SYSREF_MUX = 3       # Continuous SYSREF mode.
    SYSREF_CLKin0_MUX = 0  # Feed SYNC/SYSREF path from SYSREF_MUX
    SYSREF_REQ_EN = 0    # No SYSREF REQ mode.
    SYSREF_PLSR_PD = 1   # Don't need the pulser.
    SYSREF_CLR = 0

    Naveen kumar A

    I am generating 156.25 MHz from DCLK2 and 19.53625 MHz from SDClk3 and the same is generated from DClk12 and SDClk13. Both Dclk and SDClk are in LVDS standard with AC coupling capacitors.

    The JESD link between ADc and FPGA fails randomly. Some times Sync pin is always low and sometimes Sync pin toggles.

    Can you please help in identifying reason for that?

    I don't have enough information to assist here.  Is this in a continuous SYSREF mode?

      > Note in general you don't want to use continuous SYSREF.  Having SYSREF continuously running consumes power and creates risk of crosstalk.  However if you just turn on and then off for synchronization, that's ok.

    Naveen kumar A
    I want Dclk to be generated when I configure LMK04828 and Sysref to be generated after I configure ADC and JESD Receive core.

    I would program the device for pulser mode, configure the device.  Then when you need to sync, request a sequence of SYSREF pulses.  I guess if you are AC coupled, this may not work for you... in which case I would setup the device for pulser, never give the pulses, but then toggle the SYSREF_MUX between pulser and continuous mode as required for turning on or off sysref.

      > Do you have any interest in DC coupled SYSREF to the ADC12DJ3200?

    73,
    Timothy

    ____________________________________________________________________________________

    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

  • In reply to Timothy T:

    Hi Timothy,

    I am writing as per below mentioned order.

    R0 (INIT) 0x000090
    R0 0x000000
    R2 0x000200
    R3 0x000306
    R4 0x0004D0
    R5 0x00055B
    R6 0x000600
    R12 0x000C51
    R13 0x000D04

    ##1
    R256 0x010010
    R257 0x010155
    R258 0x010255
    R259 0x010300
    R260 0x010420
    R261 0x010500
    R262 0x0106F9
    R263 0x010700

    ##2
    R264 0x010810
    R265 0x010955
    R266 0x010A55
    R267 0x010B00
    R268 0x010C20
    R269 0x010D00
    R270 0x010EF0
    R271 0x010F11

    ##3
    R272 0x011010
    R273 0x011155
    R274 0x011255
    R275 0x011300
    R276 0x011420
    R277 0x011500
    R278 0x0116F9
    R279 0x011700

    ##4
    R280 0x011810
    R281 0x011955
    R282 0x011A55
    R283 0x011B00
    R284 0x011C20
    R285 0x011D00
    R286 0x011EF9
    R287 0x011F00

    ##5
    R288 0x012010
    R289 0x012155
    R290 0x012255
    R291 0x012300
    R292 0x012420
    R293 0x012500
    R294 0x0126F0
    R295 0x012710

    ##6
    R296 0x012810
    R297 0x012955
    R298 0x012A55
    R299 0x012B00
    R300 0x012C20
    R301 0x012D00
    R302 0x012EF0
    R303 0x012F11

    ##7
    R304 0x013010
    R305 0x013155
    R306 0x013255
    R307 0x013300
    R308 0x013420
    R309 0x013500
    R310 0x0136F0
    R311 0x013710


    R312 0x013801
    R313 0x013903
    R314 0x013A00
    R315 0x013B80
    R316 0x013C00
    R317 0x013D08
    R318 0x013E03
    R319 0x013F00
    R320 0x01408B
    R321 0x014100
    R322 0x014200
    R323 0x014311
    R324 0x014400
    R325 0x01457F
    R326 0x014608
    R327 0x01471A
    R328 0x014802
    R329 0x014942
    R330 0x014A02

    R331 0x014B16
    R332 0x014C00
    R333 0x014D00
    R334 0x014EC0
    R335 0x014F7F
    R336 0x015003
    R337 0x015102
    R338 0x015200

    R339 0x015300
    R340 0x015478
    R341 0x015500
    R342 0x015678
    R343 0x015700
    R344 0x015896
    R345 0x015904
    R346 0x015AB0
    R347 0x015BD4
    R348 0x015C20
    R349 0x015D00
    R350 0x015E00
    R351 0x015F0B

    R352 0x016000
    R353 0x016104
    R354 0x016245
    R355 0x016300
    R356 0x016400
    R357 0x01650C
    R369 0x0171AA
    R370 0x017202

    R380 0x017C15
    R381 0x017D33
    R358 0x016600
    R359 0x016700
    R360 0x016819
    R361 0x016959
    R362 0x016A20
    R363 0x016B00
    R364 0x016C00
    R365 0x016D00
    R366 0x016E13
    R371 0x017300

    After this I am again writing below registers to generate sysref. While I am doing this the both DClk and Sysref are also going off and coming again.

    0x13900, 0x14391, 0x14400, 0x144FF, 0x14310, 0x13903, 0x1FFD00, 0x1FFE00, 0x1FFF53

    I don't have enough information to assist here.  Is this in a continuous SYSREF mode?

    Yes, this is in continuous SYSREF mode.

    I would program the device for pulser mode, configure the device.  Then when you need to sync, request a sequence of SYSREF pulses.  I guess if you are AC coupled, this may not work for you... in which case I would setup the device for pulser, never give the pulses, but then toggle the SYSREF_MUX between pulser and continuous mode as required for turning on or off sysref.

    Kindly suggest sequence of registers to be written with value.

    Do you have any interest in DC coupled SYSREF to the ADC12DJ3200?

    Yes.

  • In reply to Naveen kumar A:

    Hello Naveen,

    Naveen kumar A
    0x13900, 0x14391, 0x14400, 0x144FF, 0x14310, 0x13903, 0x1FFD00, 0x1FFE00, 0x1FFF53

    This appears good to prevent the DCLK/SYSREF from turning on off at the SYSREF frequency as you've set 0x144FF -- sync disable to all dividers.

    I notice you've set the SDCLKoutY_DDLY = Bypass.  I do not suggest that.  That is primarily for if you want to route CLKin0 to SDCLKoutY directly.  At least set to 2 cycles.  (0x10c22) for SDCLKout3.

    Naveen kumar A
    Kindly suggest sequence of registers to be written with value.

    Hmm.  The registers you have appear as if they should do the job.  When you say the DCLK and SYSREF are turning on and off...  can you share a scope plot of this?

    Naveen kumar A

    Do you have any interest in DC coupled SYSREF to the ADC12DJ3200?

    Yes.

    So the requirement for DC coupling is to reduce the Vcm of the clock signal to an acceptable level for the receiver.  The LCPECL output mode has been designed to provide a relatively high swing with a relatively low Vcm.  It's not low enough Vcm for the ADC12DJ3200 at about 1.1 V.  However it allows you to then created a voltage divider using the emitter resistors which have been broken into Rs + Rb.  The LCPECL can be divided down from the 1.1 V Vcm to 0.5 V Vcm while still maintaining differential swing levels required.

    73,.
    Timothy

    ____________________________________________________________________________________

    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html