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LMK04828: Multiple RFSoC Clock Tree Synchronization

Intellectual 810 points

Replies: 7

Views: 93

Part Number: LMK04828

Hi All,

Could someone validate the clock scheme used for Multiple RFSoC synchronization

Will i be able to achieve <5 degree phase variation for all clock inputs across each RFSoC ?

  • Hello Shekhar,

    < 5 degrees of 6 GHz is... ~2.3 ps.  I do not think you will be able to achieve that over PVT.  You may be able to use the ability to do fine phase adjust in the LMX2594 to tune to that level.

    Since you are not re-clocking a SYSREF through CLKin0, you will need a SYNC signal to both LMK04832 to request a SYSREF at the same time to cause each LMK to generate a SYSREF at the same time.

    73,
    Timothy

    ____________________________________________________________________________________

    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

  • In reply to Timothy T:

    Hi Timothy

    Since I am providing Ref Clock as 5MHz with length matched to all LMK's , I expect all SCLKout to be in phase.

    Then what is the need of providing external SYNC to each LMK

    I do not have any such provision in my design

    Please provide your feedback

  • In reply to Shekhar Kulkarni:

    Hi Timothy

    Is my below understanding correct ?

    "

    Do we need all SYSREF for RFSoC to occur at same edge and also at same moment ?

    If same edge, not same moment, Then no Sync is needed for all SYSREF to occur at the same time

    If same edge and same moment, then we will need to request SYSREF at the same time from all the down-stream LMK04828 devices

    "

  • In reply to Shekhar Kulkarni:

    Hi Shekhar,

    Shekhar Kulkarni
    Do we need all SYSREF for RFSoC to occur at same edge and also at same moment ?

    Not for the purpose of JESD204B alignment.  Only if you add this requirement.  JESD204B determinism only exists within the LMFC.  Beyond that you must keep track of the timing.

    So with the 0-delay at the SYSREF frequency.  So if you send SYSREF and reset the LMFC of one converter.  Then in 5 minutes send SYSREF to reset another converter.  From JESD204B perspective it will be as if the first converter received a SYSREF at the same time as when you send the second SYSREF 5 minutes later.

    73,
    Timothy

    ____________________________________________________________________________________

    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

  • In reply to Timothy T:

    HI Timothy,

    When configuring digital delays to align the SYSREF and clock outputs [Useful for trimming out routing delays or aligning the SYSREF output to the center of a valid window on the data clock], do we need to provide SYNC input, and on which pin of LMK ?

    If yes, will it be from a Master LMK device ?

  • In reply to Shekhar Kulkarni:

    Hello Shekhar,

    You do not need to synchronize when making adjustments to the field SDCLKoutY_DDLY.  If you change the global SYSREF digital delay (SYSREF_DDLY) or the device clock digital delay (DCLKoutX_DDLY_CNTL/CNTH) you will need to provide a SYNC.
      - To do the sync to update the DDLY, the simplest thing is to provide software SYNC.  You will need to set all SYNC_DIS = 0.  0x144 = 0x00.  Then set SYSREF_MUX to normal.  Toggle the SYNC_POL.  Then you can flip back to the prior config and set 0x144 = x0ff again.
       - Please refer to datasheet section 9.3.2.
       - LMK04832 TICS Pro profile will generate a register sequence to program under the frequency planner tab at the bottom... this is for LMK04832.  However the register maps are similar.  It may work for you.
       - Finally, please take a look at: