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LMK03806: Using clock generator or similar device as delay generator

Young He
Prodigy 20 points
Part Number: LMK03806
Other Parts Discussed in Thread: LMK04808, LMK04832, LMK04828

Hello,

I am currently making a high speed camera, and I would like the time delays between exposures (independently variable) to be controllable to within 1 nanosecond or better. If I am reading the datasheet correctly, the LMK03806 and similar clock generators can provide a very accurate clocks through the use of frequency dividers, and the SYNC contact can synchronize all the clocks. 

Basically what I need is the clocks to all start running (or be reset) when I set the sync pin high to within a fraction of a nanosecond. The first rising edge of the fastest clock will trigger the first exposure, the rising edge of a slower clock will trigger next, etc. Does the synchronization have a high enough jitter that I will not be able to accomplish the proper timing? 

If this clock will not work, would it be possible to recommend another device that will satisfy my requirement? Thanks for the help. 

  • 0
    TI__Mastermind 28530 points

    Hello,

    The SYNC pin would allow you to release the output clocks to operate at different frequencies to accomplish what you would want if you could ignore the first common rising edge.  Further, there will possibly more latency than 1 ns between SYNC de-assert and output clocks due to some pipelining.

    I suggest using an LMK0480x (LMK04808) or LMK04832 device as clock generator to accomplish what you would like because you could then use the same frequency, but adjust the digital delay offset as illustrated in figure 12 of the LMK04808 datasheet on page 35.  Digital delay timing between the clock outputs can be adjusted digitally with a granularity of half a period of the VCO frequency.  So if you used 3000 MHz as a VCO frequency, the 0.5 / 3000 MHz = 166.66.. ps would be the resolution of the adjustment you could make.  Technically you could do this with different divide values.

    As for the resolution of your timing, the rms jitter specification is the standard deviation variation expected from a clock edge.  Therefore given an RMS jitter of 100 fs, 68.2% of your clock edges will fall within 100 fs of your target time.  95.4% will fall within 200 fs of your target time.  Please refer to Chooinsg Loop BW for PLLs in the Clock & TIming files section which illustrates this on slide 8.  The only catch for you is what is the integration bandwidth to use.  See slide 41 and beyond.  I think the length of time for all your camera triggers would correspond to the low integration range while the time between camera triggers would correspond to your high integration range.

    One more part number, the LMK0482x (LMK04828) may have the lowest latency SYNC when using CLKin0 as the sync path to the dividers with the SYSREF_CLKin0_MUX selecting the CLKin0 input directly.  This will cut down on some of the latency caused by re-clocking of SYNC signal.

    73,
    Timothy

  • 0 in reply to Timothy T
    Prodigy 20 points

    Thanks very much for the help and the very clear explanation. It would never have occurred to me to use the LMK04808 chip you suggested for the delay generator.