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LMK03806: LMK03806 output high jitter

Part Number: LMK03806
Other Parts Discussed in Thread: LMK03328, LMK03318

On our board,we use two LMK03806s.

When two LMK03806s internal VCO is configured to 2578M, the output clock 322M has high TIE jitter which is about 1.3ns.see attached file "LMK0-322(VCO 2578)_LMK1-156(VCO 2578)"

When one LMK03806 internal VCO is configured to 2578M and another LMK03806 internal VCO is configured to 2500M , the LMK03806  that internal VCO is configured to 2578M outputs 322M low TIE jitter which is about 18ps.see attached file "。"LMK0-322(VCO 2578M)_LMK1-156(VCO 2500) "

Two LMK03806s use different power source. there are 5000mil between the two LMK03806. Our schematic is at attachment "LMK03806BISQE".

Please analyse this problem.

ThanksLMK03806BISQE.rar

  • Hi,

    I only see one LMK03806 device in the attached schematic, can you show me where to find the second one? Just so that I'm understanding this correctly, the jitter goes up when the two adjacent LMK03806 devices have the same VCO frequency?

    Regards,
    Hao

  • Hi,

    I only see one LMK03806 device in the attached schematic, can you show me where to find the second one? 

    There are two LMK03806 devices in this attched schematic. LMK03806 device configuration file is in the attachment.

    Just so that I'm understanding this correctly, the jitter goes up when the two adjacent LMK03806 devices have the same VCO frequency?

    No, Only when two adjacent LMK03806 devices have the same VCO 2578M frequency , the jitter goes up.

    when two adjacent LMK03806 devices have the same VCO 2500M frequency , the jitter is low. 

    0284.LMK03806BISQE.rar

  • Sorry I'm still not understanding. I can see how you generate 322MHz out of 2578MHz VCO. But how do you generate 322.265625MHz out of 2500MHz VCO?

    Regards,
    Hao

  •  I can see how you generate 322MHz out of 2578MHz VCO. But how do you generate 322.265625MHz out of 2500MHz VCO?

    I redescribe our test.

    When both device A and B generate  322MHz out of 2578MHz VCO,device A Clock jitter goes up.

    When device A generate  322MHz out of 2578MHz and device B generate 156MHz out of 2500MHz,device A Clock jitter is low.

    When both device A and B generate  156MHz out of 2500MHz VCO,device A Clock jitter is low.

     

     

     

  • The reason why 322MHz has higher jitter is that the PFD (Phase Frequency Detector) frequency is very low in order to generate this VCO frequency. The output phase noise is directly related to PFD frequency. The higher the PFD frequency the better the output phase noise.

    For example, with 2578MHz VCO, the PFD frequency = 3.125MHz, but with 2500MHz VCO, its PFD frequency = 50MHz

    Another reason may be that the external loop components are suitable for 2500MHz VCO, but not optimal for 2578MHz VCO. If you have a phase noise analyzer, this will be clear after measuring its phase noise plot. If not, you can use PLLatinum sim to simulate the loop dynamics. The PLLatinum sim can be downloaded for free: 

    Regards,
    Hao

  • Thanks for your help

  • Do you have any solutions for a better jitter when generate  322MHz out of 2578MHz VCO?

    Thanks,

  • Hi Tong,

    The performance will probably be better if you use a fractional PLL. In that case the PFD frequency can be kept as high. We have LMK03318 and LMK03328, the only difference between the two is the number of PLLs. LMK03318 has one PLL and LMK03328 has two. For example, if you need to generate 156.25MHz and 322.265625MHz at the same time, use LMK03328. If you just need to generate one of them at a time, then use LMK03318.

    Also, we use phase noise analyzer to measure noise performance because an Oscope has too much noise by itself. The typical standard that we use for wired comms is 12k-20MHz integrated RMS jitter.

    Regards,
    Hao