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WEBENCH® Tools/LMX2572: TICS Pro bug at LMX2572: wrong Post-SR divider input frequency range

Bjoern Schormann
Intellectual 375 points
Part Number: LMX2572
Other Parts Discussed in Thread: LMX2594

Tool/software: WEBENCH® Design Tools

Hello Forum,

I think there is a bug in the TICS Pro V1.7 software with a LMX2572 device and the "Support Request" people can't help about this!

There is a discrepancy between datasheet and software tooltip about the Post-SR divider input frequency range.
Please have a look at the following picture from the software and the included datasheet table:

https://ticsc.service-now.com/sys_attachment.do?view=true&sys_id=398a75141bf46450ad92ba63164bcb7f

Goal is to use the PLL in Integer mode (for a JESD204B application) with or without phase adjustment/shift (of course is a MASH ORDER >= 2 for the latter one necessary) and additional SYSREF shifting in repeating-mode.

By the way: is the SYSREF divder value (and therefore the limits) important for the SYSREF_REPEAT mode, on the other hand the stepsize depends on the "Pre-SR divider" value?

Best regards

  • 0
    TI__Mastermind 28960 points

    Hello Bjoern,

    Your image didn't make it into the post, can you please re-upload? In case there's more image trouble, can you explicitly state the discrepancy you observed?

    In SYSREF_REPEAT mode, the SysRefReq pin is reclocked to the SYSREF interpolator frequency and then to RFoutA, so both the SYSREF_DIV_PRE and the interpolator limits should be respected. However, the SYSREF_DIV is not used in repeater mode, since the pulse width is determined by retiming the signal on the SysRefReq pin. The delay circuit is still used to set the delay from the RFoutA rising edge to the SYSREF rising edge.

    The LMX2572 documentation for the SYSREF feature appears to be incomplete. The LMX2594 datasheet section 7.3.14 includes a block diagram (Figure 30) which more clearly illustrates the SYSREF architecture re-used in the LMX2572.

    Regards,

  • 0
    Intellectual 375 points

    Here are the missing picture again:

    Inserted as picture (as before at the start entry):



    and as file link:

  • 0 in reply to Bjoern Schormann
    TI__Mastermind 28960 points

    Hello Bjoern,

    Looks like only the file link method works for uploading images.

    I'm checking internally with the team to see if we have conclusive validation data to suggest which range is correct. I anticipate the 800-1500MHz range is the correct one, since this is also the range given for the LMX2594, and the SYSREF structure for the two devices is mostly the same. Once I get a conclusive answer, I'll let you know. 

    Regards,

  • 0 in reply to Derek Payne
    TI__Mastermind 28960 points

    Hi Bjoern,

    The 800-1500MHz range is the correct one. Outside of the 800-1500MHz range for the interpolator frequency, the SYSREF delay steps will tend to become nonlinear (step sizes will vary). I believe the range in the datasheet is the range over which the SYSREF delay circuit will still function, although the steps will be highly nonlinear outside of the 800-1500MHz range. I'll note the discrepancy for our next datasheet revision pass.

    Regards,

  • 0 in reply to Derek Payne
    Intellectual 375 points

    Ok.

    Is the 800-1500MHz range limit only important for the Delay Circuit itself or for the SysRefReq Pin and the Re-clocking Circuit at SYSREF_REPAET mode too?

  • 0 in reply to Bjoern Schormann
    TI__Guru* 81400 points

    Hi Bjoern,

    Yes, this frequency range is important to the re-clocking circuit for both master mode and repeater mode.