The ADC12DJ3200EVM uses the LMX2582 for ADC clock generation. The EVM uses the same PLL loop component values as the LMX2582 evaluation board. Neither the ADC or LMX evaluation boards provide sufficient details on the loop configuration. PLLatinum Sim does however provide the details. If you start PLLatinum Sim, select the LMX2582, and click "Load Device", the loop components are:
C1_LF = 560pF
C2_LF = 47nF R2_LF = 150-ohm
C3_LF = 6800pF R3_LF = 12-ohm
For the purposes of understanding the design, I wanted to change the loop filter design to just a single zero and pole, but I noticed a strange error that I was able to reproduce.
If you change the "Filter Order" to "2nd Order" and then re-enter 0.56 in the C1 field, there is an error message indicating that the capacitor closest to the VCO must be larger than 1.5nF. The error message can be viewed in the screen shot below.
When "Filter Order" is "3rd Order", C3 is closest to the VCO, and since C3 = 6.8nF, the minimum value requirement is met. Since the ADC12DJ3200EVM schematic shows 6800pF on Vtune, this requirement is met on the hardware.
Where is this 1.5nF minimum capacitance value documented? I've looked through the LMX2582 data sheet and EVM users guide and have not found any details. Searches for Vtune (or 1500 or 1.5) did not show up anything obvious like a 1500pF minimum capacitance requirement on that pin. Any advice on where to find this info?
Regards,
Dave
