LMK04832EVM: Programming the EVM

Part Number: LMK04832EVM
Other Parts Discussed in Thread: LMK04832

Hii team,

We are using LMK04832 EVM and programming it using TICS PRO tool. We are using the EVM  for the first time and to have hands on experience we programmed it for CLKin1 = 122.88MHz and configured all outputs to 122.88MHz but when we probed and checked on EVM output ports 4,5,6,7,12,13 are not giving the required output. May I know the reason why the outputs are not proper. I have attached the programmed file. I also request you to help us in rectifying this issue.

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Regards,

Keerthana.

CLk122.88.tcs

  • Keerthana,

    Are you following the recommended programming sequence by toggling the RESET bit first, then writing all registers? TICS Pro should write the registers in the correct order per datasheet instructions, but does not automatically initiate the RESET.

    Additionally, your programming file has PLL1 feedback derived from the FB_MUX output, but FB_MUX is not enabled. Is this intentional?

    When you say "not proper" what does this mean? For example, are the outputs at an incorrect frequency? Missing? One leg of the differential pair is active and the other is not? We need more information about the issue.

    Have you configured the termination correctly for the desired output formats? For instance, I see that CLKout4 is configured for LVPECL, while CLKout5/6/7 are configured for LVDS. Both CLKouts 4/5/6/7 are terminated for CML by default on the EVM (50Ω or inductive pull-ups). Similarly, CLKout12/13 are configured for LVDS, but are terminated for LVPECL. Please ensure the proper termination is used for the configured output formats.

    Regards,

    Derek Payne

  • Hii Derek, we toggled the reset bit first and then wrote all the registers still we are facing the same issue. We are not getting the outputs in ports 4,5,6,7,12,13 whereas for other ports we are getting 122.88MHz as output(as required). I have attached the programmed file. It is operated in nested 0-delay mode and input to CLKin1 is 10.24MHz. Our requirement is to get 122.88MHz on all the ports. I request you to import this file into your tool and check with the evm if outputs are coming. I also request you to help us in rectifying this issue.

    Clk080421.tcs

    I also wanted to know if there is any relation between device clock and sysref clock. How to choose sysref clock for a particular device clock?

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    Regards,

    Keerthana

  • Keerthana,

    Again, have you confirmed you have the appropriate termination installed for the outputs you want to monitor?

    You say that you would like to get 122.88MHz on all the ports, but you have the SYSREF divider running and routed to several outputs:

    To convert all outputs to 122.88MHz device clock output, you must set the CLKoutX_SRC_MUX for each output to "Device Clock". Optionally, SCLKx_y_PD can also be set to disable the SYSREF path, saving current.

    Regards,

    Derek Payne

  • Hii,

    I have attached the updated file where all outputs are configured for device clock. When we probed it all other outputs are proper except port 4 and 6(outputs are missing). May I know the reason. I also request you to import this file into EVM and let us know if ports 4 and 6 are giving required outputs.

    clk090421-122.88.tcs

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    Regards,

    Keerthana

  • Keerthana,

    Per datasheet 8.1.9.7, even-numbered outputs may only be programmed to CML when in bypass mode. You must either modify the on-board terminations for the output format you desire, or observe CLKout4/6 with the divider bypassed (i.e. at 2949.12MHz). Since your application requires 122.88MHz on all outputs, I recommend modifying the EVM's on-board terminations to match the output format required by your application, and then updating the output format registers for the desired output format

    Regards,

    Derek Payne