• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 20 subscribers
  • Views 150 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CDCLVD1212: Static Outputs

Steve Widener
Genius 9595 points
Part Number: CDCLVD1212

I’m using a CDCLVD1212 and would like the option of turning “off” the outputs of the buffer.

I noticed that Table 1 of the datasheet offers an option for the outputs to be static. I didn’t find the definition of static in the datasheet.

Questions:

Does "Static" mean the outputs are high impedance, or a predetermined logic level, if the last one, do we need pull resistors to set the “static” output?

Would an FPGA high impedance output be a valid “open” for IN_SEL?

Is IN_SEL able to handle dynamic switching between a 0 or 1 and high impedance?

  • +1
    TI__Expert 5110 points

    Hello Steve,

    Table 1 mentions in the note that Input buffer are disabled and the outputs are static when IN_SEL is left 'Open', yes.

    I have not operated this device in this configuration and the datasheet does not specifically describe this configuration. Although this is the case, we are thinking the latest Logic State will be held when input buffers are disabled. 

    The IN_SEL is able to handle dynamic switching.