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LMK04832: LMK04832 distribution mode does not work

Part Number: LMK04832

I have a design which creates a 10MHz output from a 10MHz input, using both PLL1 and PLL2. However, when I change the clock distribution mux to CLKin1 (and TICS automatically changes CLKin1_DEMUX to Fin), and I update the output dividers to divide-by-1, I do not see the 10MHz output anymore.

Can you clarify what steps need to be taken to get distribution mode to work at 10MHz? Or, maybe there is a bug in TICS which would be great to know about if that is the case.