Hi,
I'm trying to use an LMK04828 in single loop mode to generate a 1GHz system clock from a 100MHz OCXO. Input to OSCin is 100MHz sine at 1.5Vpp. PLL2 is configured with R=1 and N=30 (/2 in prescaler and /15 in main divider). I've selected VCO1 which should lock at 3GHz, which is then divided down to 1GHz and some other frequencies in the output dividers. I have the loop filter as follows
- R2 = 560R external
- R3 = R4 = 200R internal
- C1 = 68pF external
- C2 = 4.7nF external
- C3 = C4 = 10pF internal
Clock Design Tool tells me this should give a loop bandwidth of 191kHz and phase margin of 68.7 degrees. My own simulations of the block diagram in SPICE give almost the exact same numbers.
Problem is the PLL refuses to lock. DLD output stays low, and the voltage on CP2OUT is a ~0.36V ramp waveform at 1.2MHz sitting just below the 3.3V rail.
I tried putting the PLL2_R and PLL2_N signals on Status_LD1 pin. PLL2_R is a clean 100MHz square as expected. PLL2_N is at 101.2MHz, which given the /30 ratio would put VCO1 at 3036MHz. Using an FFT you can clearly see the sidebands from the 1.2MHz modulation. This isn't present on PLL2_R, that's dead clean.
This looks like loop instability but I don't understand why given that CDT says I have plenty of phase margin. I've checked that PLL2 is set for negative slope (PLL2_CP_POL=0) and OSCin_FREQ=1 for 100MHz input.
I also noticed I get nothing on any of the DCLKx and SDCLKx outputs even though they should be enabled. I don't see anything in the datasheet that says these are disabled until the PLL locks. Is this normal or could it point to some bigger problem?
Thanks,
Tom