Do Out0 and other clocks derived directly from refclk have a jitter measurement?
Do the dividers preserve any jitter spec when the PLL is powered down and use refclk?
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Do Out0 and other clocks derived directly from refclk have a jitter measurement?
Do the dividers preserve any jitter spec when the PLL is powered down and use refclk?
Hello,
Yes there's max additive jitter of 350fs:
You can do RMS addition to calculate the final jitter. For example, if the input jitter is 500fs, then the total jitter is sqrt(500^2 + 350^2) = 610 fs.
Regards,
Hao