LMK04832-SP: Can this device operate with standard 4-wire SPI?

Thanks Derek for the very timely answers!

They resolved pretty much everything I originally asked.

I am still unclear during power-up how the device actually gets reset. The datasheet simply doesn’t appear to describe this that I’ve seen.

We would want to be sure that the device powers up and resets correctly to the published defaults without need of writing the reset register.

Are there any available details relating to power-up and reset operations at the hardware level?

A new related question comes from pg 12 of the datasheet where it states “4-wire mode read back has same timing as SDIO pin”.

I find this a tiny bit suspicious as some of the mux selectable outputs for 4-wire SPI are on different edges of the package than SDIO.

I can see how the statement can be accurate under a couple of conditions:

1. The clock-to-out delays on all of those possible pins are the same
2. The t_DV value of 120ns simply envelopes all of the possible pins

Just wanted to confirm.

Is there any minimum value available for t_DV?

Thanks,

Dan

Dan,

I'm confirming internally the behavior of POR, RESET bit, and RESET pin. In general, when the device powers up, there is a period of time at startup where all the LDOs are powering up and stabilizing across the device. We have an on-board ~10MHz oscillator on the digital clock which counts out some number of cycles for the system to load all the registers with the default values programmed in metal, and as far as I know the only difference between POR and bit/pin reset is the addition of some time or some other equivalent mechanism to allow the LDOs to settle at startup. Exactly how this works, and how long it takes, as the timings are not captured in the datasheet - hence why I am confirming internally. If my suspicions are correct, you don't need to do anything except power up the device to ensure that the default values are properly loaded.

SDO being at different edges of the package might introduce 1-2ns timing difference. We've set the tDV max value at 120ns, and since SCK is limited to 2MHz (500ns period, 250ns from falling edge to rising edge) the readback value will always be stable on the next SCK rising edge. I can't say for certain, but I suspect the 120ns number is sandbagged as well, to help guarantee behavior across PVT for even the most exceptional of cases.

In the absence of a printed minimum value, I will appeal to causality: the falling edge of SCK triggers the data to update for readback, so I suggest the lower limit is 0ns.

Regards,

Derek Payne

Thanks again Derek,

I’ll let you chase the reset thing a bit but it seems power-up and forget it.

As for the minimum clock-to-out I would have assumed 0 as well in the absence of a value even thought we know it is always >0.

The challenge here is that it can make meeting hold time difficult (particularly when SI inegtrity tools produce a legitimate negative trace delay based on an IBIS model).

Someone wishes to connect the RESET/GPO to have available for a hardware driven reset so we will use pin 48

RESET by naming convention appears to be active high and can be confirmed in Table 8-46 for register 0x14A .

RESET_TYPE can be configured to include an internal pulldown (default) or pullup and no approximate value for these pulls is available.

I would typically pull the an active-high reset input low externally with a fairly stiff value like 1K.

I want to be sure this would not impact the normal device reset at power up though it seems unlikely since the default is pulled down anyhow.

Another new observation:

Sections 6.1 and 6.3 define VDD and VDD_A.

The electrical characteristics tables in section 6.5 all report their values are for VDD=VDD_A=3.3V

The actual parametric data in the tables is all using a generic value of Vcc.

The device pins use Vcc1-Vcc12  with a descriptor following such as Vcc5_DIG.

I assume all 12 Vcc pins use 3.3V, for example on pg 11 Digital Outputs, VOHmin is Vcc-0.4 meaning VDD-0.4.

Can any of the 12 Vcc pins be left disconnected if an entire related group (see Figure 5-1) would be left unused?

VDD_A is defined as the “core” voltage yet none of the 12 Vcc* pin descriptions mentions a core voltage.

I’m assuming the core voltage comes from Vcc3_SYSREF based on Figure 5-1 – is that correct?

Regards,
Dan

Hi Dan,

I determined that the reset behavior is identical for register, pin, and POR resets (though, interestingly, after writing RESET=1, the device will remain in the RESET state until the start of the next SPI transaction). That said, there should be no impact to POR if the reset pin sees noise at startup - the reset sequence will just start over. A stiff external pull-down value is not strictly required given the internal resistance, but remains a good idea.

All VCC pins must be connected to 3.3V, even if something is unused. The VDD_A and "Core supply" language may be a poorly-explained attempt to distinguish between VCC5_DIG (all digital I/O powered from this supply) and the other VCC pins. (In which case why wasn't VDD_A referred to as VCC5_DIG? Probably because we called it that in another datasheet and it got copied...) Treat them as the same supply for all intents and purposes, since I am certain we never individually varied any specific pin voltagess with respect to others as the artificial distinction here implies.

There are register settings which can powerdown large sections of the LMK04832-SP, and this is the recommended method for reducing power consumption. Many unused rails can approach 0mA consumption after the appropriate register settings are specified.

For our parametric data, we ensured that the supply voltage at the device pins was 3.3V as closely as possible, though some supplies draw slightly more than others so there can be some ~10mV difference at test time. All parameters have also been characterized to 3.3V ±5% on all supplies.

Regards,

Derek Payne