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LMK04610: LMK04610 Configuration

Ed Gouweloos
Intellectual 260 points
Part Number: LMK04610
Currently we are using the LMK04610 in our design, we are using the
SIT3808AI-CF-33EM-50.000000X as VCXO and the DSC1101DL5-050.0000 as CLKIN1.
At the CTRL_VCXO there is a 100nF capacitor.
What we see is that the PLL1 lock-detect is active and the "falls out of lock after ~ 75ms".
Then the PLL1 locks again, and so on.
Please find attached the TICS-PRO configuration file, can you please check this and see where
we have failed?LMK04610_2021b.tcs
  • 0
    TI__Mastermind 29010 points

    Hi Ed,

    This sounds like either an issue with the switch between fastlock coefficients and final coefficients, or the lock detection circuit is misbehaving.

    Have you tried using the PLL1 loop filter tool page to set the bandwidth for PLL1? Try configuring the device for something like 20Hz and see what coefficients are recommended. I get much less proportional gain than what you are using. You could also try adding a small amount of integrator gain (1-2) to your current setup.

    Have you checked that CLKIN and OSCIN frequencies are actually drifting in phase when the device reports unlock condition? If they are actually phase aligned, it may just be a lock detect reporting issue and we could look for configuration issues with lock detect.

    Regards,

    Derek Payne

  • 0
    Intellectual 260 points

    Hi Derek,

    Thanks for your answer.

    It is a bit tricky to measure at the device (not accessible) so I can not provide you with phase details right away.

    Could you provide me with the correct settings for PLL1 and if in case I am not really interested in the absolute
    quickest way to "lock", could you provide me with the fastlock-settings that are "full-proof/fool-proof". To my knowledge, fastlock is not enabled
    in our config. Regarding the lock detect, you have the configuration file and as far as I know the lock detect windows is at its "widest".

    Anyway, if you could provide me with better settings for PLL1 I would appreciate it very much, then over the weekend I will try to connect some
    wires for the signals that you have requested.

    Kind Regards

    Ed

    For the

  • 0 in reply to Derek Payne
    Intellectual 260 points

    Hi Derek,

    Thanks for your answer.

    It is a bit tricky to measure at the device (not accessible) so I can not provide you with phase details right away.

    Could you provide me with the correct settings for PLL1 and if in case I am not really interested in the absolute
    quickest way to "lock", could you provide me with the fastlock-settings that are "full-proof/fool-proof". To my knowledge, fastlock is not enabled
    in our config. Regarding the lock detect, you have the configuration file and as far as I know the lock detect windows is at its "widest".

    Anyway, if you could provide me with better settings for PLL1 I would appreciate it very much, then over the weekend I will try to connect some
    wires for the signals that you have requested.

    Kind Regards

    Ed

  • 0 in reply to Ed Gouweloos
    Intellectual 260 points

    Hi Derek,

    My apologies for not responding earlier.

    I have been measuring over the weekend and concluded that the pull-range of the VCXO was too small.
    Fortunately I could replace that one with a VCXO with a larger pull-range and that solved the
    "lock-detect" problem. So in fact the lock-detect did exactly what it should be doing.

    Thanks,
    Ed

  • 0
    Prodigy 20 points

    In my opinion You must eneble PLL1_LOL_NORESET parameter on PLL1 settings.