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CDCE913: CDCE913PW to be a VCO for video genlock

Part Number: CDCE913

Hello Team,

I have a very technical query relayed from my customer about how increasing and decreasing output frequency is done on this device. Please see the full description of customer's case below:

I have a certain video scaler IC which supports genlock function. It measures phase difference between V sync of source video with V sync of output video, then outputs a PWM signal accordingly. this PWM signal is fed through a buffer + voltage divider to CDCE913PW IC @ Vctr pin (tied to pull up resistor too). VDD=1.8v, VDDOUT=3.3v, crystal is 27MHz.

S0 is tied to 1.8v, while S1 and S2 to I2C lines. it uses Y1 and Y2 outputs (tied together) and feed this back into the IC itself as it takes the increase\decrease of frequency to achieve the genlock function.

my issue is that I failed to understand how CDCE913PW works in this case. I mean how to let it automatically increase\decrease its output frequency based on the input voltage explained above?

Thanks for your support.

Regards,

Archie A.

  • Hello Archie,

    I am not quite understanding where the output of the device is being utilized. The CDCE913 device itself is meant to be a Low Power LVCMOS Clock Generator with internal PLL.

    The Vctrl pin is meant to be utilized with a crystal (XO) input to Xin/CLK and Xout. As Vctrl moves from 0V to 1.8V this frequency can change +/- 150 PPM depending on the crystal selected.

    Again, this change of PPM is done through the changing of the VCTRL - control voltage. I would highly suggest that you read through this Application Note - SCAA085A. Please note section 3.3.

    Let me know if there are additional questions after this.