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LMK03318: Clock input instability

Harald Saether
Prodigy 10 points
Part Number: LMK03318

I am using LMK03318 and experiences an instability on the ref clock. It is configured to use PRIREF in single-ended mode, 10MHz, 3V3 signal. PRIREF_N is connected to GND. The PLL is not in lock.
I am routing the PRIREF to Output7 with CMOS(+/HiZ) . The output of this is shown in Red together with the input clock Green.  I don't understand what is going on here. It seems like a transition problem and that a flip-flop is involved. When PRIREF is routed to output I was expecting a buffered version only. The input clock is very clean without and reflections or bad flanks(as shown in Yellow). Any idea what is going on and what is wrong?

  • 0
    TI__Mastermind 18070 points

    Hello,

    Can you check if the PLL is locked by correctly configuring the status pins in Ticspro and measuring the status pin voltage?

    PLL LOL means PLL Loss Of Lock.

    Additionally, do a soft reset to recalibrate the VCO after writing all registers. You can see what was done in the log window of Ticspro.

    Use the wizard to correctly calculate frequencies.

    Regards,

    Hao

  • 0 in reply to Hao Z
    Prodigy 10 points

    Hello,

    Shown plot is with the proposed settings. The problem is still present. 

    Yellow is input clock, 10MHz, 3V3. Also measured is 20/80 rise fall time to 1.5 ns => Slew rate > 1V/ns
    Red is PRIREF to Output7 with CMOS(+/HiZ) 
    Blue is Status1 configured to PLL LOL, Push-Pull, Active Low, Fast. 
    A "Soft Reset" is applied. 
    The Status1 pulse appears with a few seconds interval. 
    PRIREF doubler is enabled. 

    Disabling the doubler gives no output after "Soft Reset"

    Power supplies: 
    VDD_IN, VDD_PLL, VDD_LDO, VDD_DIG are measured 3.35V, ripple < 2mV. 
    VDDO is measured to 1.77V, ripple < 2mV. 
    PDNn has 100nF and both 3V3 and 1V8 is stable 16ms before PDNn is reaching 1V2.
     

  • 0 in reply to Harald Saether
    TI__Mastermind 18070 points

    Hi Harald,

    So PLL LOL is always active which means PLL is never locked. Can you upload the configuration (.tcs format) you are using? (In Ticspro, File -> Save).

    Regards,
    Hao

  • 0 in reply to Hao Z
    Prodigy 10 points

    Attached is the tcs configuration file:

    Regards
    Harald

    LMK03318_10M_V0.42.tcs

  • 0 in reply to Harald Saether
    TI__Mastermind 18070 points

    Hi Harald,

    The configuration looks correct to me. I can't tell what's causing the problem. Can you try enabling the input termination and/or changing the input buffer to differential?

    Regards,

    Hao

  • 0
    Prodigy 10 points

    Below plot is Yellow input to LMK03318 with diff term enabled. (Measured 1mm from pin with 0.9pF active probe), red is Output7 CMOS+. Blue is lock detect push-pull. The PLL is now in lock. The PLL seems to operate as expected and phase Noise is as expected. I have also tried a faster buffer, this also makes the PLL operate as expected. 
    The stackup of the board is a 8 Layer board with 2 GND layers on L2 and L5. The Pad of LMK03318 has 24 Via's to GND. 

  • 0 in reply to Harald Saether
    TI__Mastermind 18070 points

    It looks like the problem is with the input buffer. You can use below settings to read back the input validation status:

    In the tool bar, there's "read all registers" to read back status registers.

    Regards,
    Hao

  • 0
    Prodigy 10 points

    Hello,

    I am Appling new setting of Reference Input Detection and doing a "Soft Reset" then "Read Status Registers"
    I get the result as shown in figure. Same result with "+Slew rate detect" and "-Slew rate detect". PLL is not in lock. 
    Using input termination makes the PLL lock. The Reference Input Detection is always the same with RISE_VALID and FALL_VALID set. 

    Regards
    Harald