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LMK04832: Clock relation and their frequencies

jimmy xu1
Intellectual 490 points
Part Number: LMK04832
Other Parts Discussed in Thread: TIDA-01442, LMX2582, ADC12DJ3200

TI has a high speed data acquisition reference design (Document number (TIDA-01442). In that design, LMK04832 and  LMX2582 use a local 100 MHZ oscillator producing "FPGA_JESD_CLK_A", "FPGA_JESD_CLK_B", "FPGA_JESD_SYSREF", and "SYSREF" for ADC12DJ3200. Could you let me know what frequencies these clock signals are in order to acquire analog signal at 3.2 GSPS sampling rate?

Thanks,

Jimmy

  • 0
    TI__Mastermind 28990 points

    Hi Jimmy,

    There are a number of different possible frequencies which could satisfy an analog signal at 3.2 GSPS sampling rate, though I am not sure which specific one the reference design implements. You may want to take a look at datasheet table 19 for the ADC12DJ3200 which suggests the JESD configurations that are possible for a system. Meanwhile I will try to get someone who worked on the design to respond.

    Regards,

    Derek Payne

  • 0
    Intellectual 490 points

    Hi Derek,

    We are referring to TI reference design (Document number (TIDA-01442) for our application schematic design. We would like to understand the details of TI reference design so our design would not have a surprise at the time of board bring up and test. It will be really helpful if you could connect me with your TI guys who involve in the reference design.  You can send my company email address to them so we could have the channel for communication.

    Thanks and really appreciate your help and support.

    Best Regards,

    Jimmy

  • 0 in reply to jimmy xu1
    TI__Mastermind 28990 points

    Jimmy,

    I believe the team that owns the reference design is in Dallas and is done working for today, but I've reached out to them. Once I'm sure who the right owner is, we can loop you into email discussion.

    Regards,

    Derek Payne

  • 0
    Intellectual 490 points

    Hi Derek,

    Great. I look forward to speaking with your reference design engineers.

    Thanks and Best Regards,

    Jimmy

  • +1 in reply to jimmy xu1
    TI__Mastermind 28990 points

    Hi Jimmy,

    I've attached a spreadsheet and configuration files provided by the design owners.

    ADC12DJxx00 EVM Clock Frequency Calculations A RTM Simplified.xlsxConfiguration Files.zip

    The design owners also provided the following context:

    • Cell K4 is the input clock frequency from the LMX chip.
    • Column M is the SYSREF frequency needed for the ADC and FPGA. The SYSREF divider is in columns N and O.
    • Column Q is the required FPGA clock frequency. The FPGA clock divider is in columns R and S.
    • Column P is for a different FPGA (Intel) not used in this reference design.

    Since we're continuing the conversation over email, I'll mark this thread as resolved.

    Regards,

    Derek Payne