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LMK1C1102: Output Enable Time Clock Cycles

Part Number: LMK1C1102

Regarding the Output Enable Times (spec shown below):

Will this “eat” up clock cycles even if the OE pin is always pulled high via pull-up resistor to VCC on power-on?

 

Thank you!

  • Hi Cassidy,

    t1G_ON/OFF will occur each time it is triggered. If the OE is always pulled high, then the 5 cycles for t1G_ON will only take place once upon power on.

    Regards,

    Jennifer

  • Does the statement you make apply when the enable is pulled high/powered-on long before the input has begin toggling?

    We can't lose clock cycles as this is used for a communication protocol clock.

    Would we lose any clock cycles under the following scenario:

    1. Device is powered on and OE is pulled high ; No clock on input
    2. Some delay or period of time that exceed the "Start-up time before output is active" as specified in datasheet
    3. Input Clock begins toggling
      1. This is where we expect the first input clock cycle to also appear on the output
      2. Given the propagation delay of 3ns, which is rather low, and the fact that this is not a PLL based device, I would expect ALL clock edges, including the first clock cycle, to be propagated to the output, assuming that the device was enable long before the first clock cycle.
      3. Can you confirm?

    Thank you!

  • Hi Cassidy,

    OE depends on CLKin. If there is no CLKin, then t1G_ON won't occur until there is a CLKin signal.

    1. No.

    2. No.

    3. Yes. t1G_ON will take place when CLKin start toggling. After that time, the outputs will output a signal.

    Regards,

    Jennifer