Regarding the Output Enable Times (spec shown below):
Will this “eat” up clock cycles even if the OE pin is always pulled high via pull-up resistor to VCC on power-on?
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Does the statement you make apply when the enable is pulled high/powered-on long before the input has begin toggling?
We can't lose clock cycles as this is used for a communication protocol clock.
Would we lose any clock cycles under the following scenario:
OE depends on CLKin. If there is no CLKin, then t1G_ON won't occur until there is a CLKin signal.
3. Yes. t1G_ON will take place when CLKin start toggling. After that time, the outputs will output a signal.