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10 kHz disciplined 40 kHz, 80 kHz and 120 kHz clock synchronisation

Other Parts Discussed in Thread: LMK05318, LMK04208, LMK04832, LMK5C33216, LMK01801, LMK5B12204, PGA280, LMK5C33216EVM


I have a jittery 10kHz reference clock that I want to use to generate/discipline a number of synchronous clocks in the tens of kilohertz range (e.g. 40 kHz, 40 kHz with a bit of phase, 80 kHz, 120 kHz).

I have evaluated the LMK05318 but, unfortunately, this only has one usable output in the kilohertz range. What device would you recommended?



  • Hi Steve,

    There are not many options for the frequency range you request.

    1. LMK04832 can directly accept 10kHz at the CLKin inputs. Using 10kHz on CLKin0 and a 30.72MHz VCXO fed back through CLKin1 (the Fin path), you could lock PLL1 and generate 40kHz, 80kHz, and 120kHz on the outputs, with digital delay adjustable in 0.5/30.72MHz = ~16.28ns steps on all outputs. This option has the lowest jitter, but there's ways to implement the same architecture using lower-cost devices with higher jitter such as LMK04208 using the feedback mux (albeit with undisclosed settings). In either case, the analog loop filter would need to be sizable to accommodate the 10kHz phase detector frequency. This is probably the simplest option, since it only requires one device.
    2. If the DPLL functions are required, there is one device (the LMK5C33216) that could directly generate all the requested output frequencies from APLL3, including the phase shift. This device is very expensive, and includes lots of other frequency domains which are not needed to satisfy your requirements. Additionally, only two outputs on the LMK5C33216 are capable of driving LVCMOS. While you did not state any output format requirement, this seems like a noteworthy limitation to include given the frequency range. I suppose at 120kHz a comparator on the output of a DC LVDS signal is probably sufficient, but it is more components and higher cost.
    3. A buffer could be added to the output of the LMK05318. We have a device, LMK01801, which is a buffer/divider that could satisfy the frequency plan, and which has two outputs that can be delayed by digital or analog means. LMK05318 would generate 6144MHz in PLL2. From there, it is somewhat tricky to satisfy the 2 x 40kHz with phase shift requirement, but it is not impossible: 6144/(4 * 200) = 7.68MHz can be driven into CLKin1 of the LMK01801, where 7.68/(8*8) = 120kHz on CLKout8-11, and 7.68/(8*24) = 40kHz on CLKout12/13 with digital delay up to 0.5/7.68MHz = about 65ns digital delay steps can be utilized. Meanwhile, the extended divider can be used to divide down 2.56MHz or lower, which can drive CLKin0 of the LMK01801 to generate another 40kHz and the 80kHz signals. It is however worth noting that one of either 40kHz or 80kHz would not be possible to generate as LVCMOS with this scheme, since CLKout0-3 on LMK01801 does not have LVCMOS available; instead, you could generate two 80kHz clocks and add a low-cost discrete D flip-flop divider stage yourself to get entirely LVCMOS, perhaps with a few nanoseconds of phase error.
      1. If a few nanoseconds of phase error is still a problem, but LVCMOS is required, this same scheme would also work with a comparable flip-flop attached to every needed output. For greater simplicity, a quad flip-flop with LVCMOS positive outputs connected to data and LVCMOS negative of a 240kHz clock, could be cascaded to produce 120kHz output; an 80kHz output could be connected and cascaded with the remaining flip-flop to produce a 40kHz clock. The 40kHz phase shifted clock would not need this retiming, since it could just be adjusted using digital and analog delay. A scheme like this which shifts an additional divide stage to an external flip flop also has the benefit of permitting the use of LMK5B12204, which lacks a low-frequency divider but saves a few dollars over LMK05318 - since now every frequency can be constructed from two 5.12MHz clocks, equal to 6144/1200 and achieved with post-divider of 6 and clock divide of 200. Of course this scheme still has the drawback that you need three devices to make four clocks.


    Derek Payne

  • Hi Derek - thank you for a very comprehensive reply.

    My output jitter requirements are fairly relaxed: < 1 ns but I'm not overly-constrained by budget either (ease of use and time to market are more important).

    I shall be independently clocking a DAC and ADC (plus the delta-sigma clock if use that type of ADC) at rates in the tens or hundreds of kilohertz (40, 80 120 were just arbitrary numbers) but these rates must be synchronised to the recovered reference 10 kHz input.

    I may use something like a PGA280 or other zero-drift device which, I believe, would also benefit from being clocked synchronously too.

    I will also need a 10 kHz output to serve as a CPU interrupt when the reference signal cannot be derived. So, in summary (for example):


    10 kHz


    10 kHz (CPU interrupt)

    80 kHz (LDAC)

    120 kHz (CONV)

    1 MHz (PGA280 clk)

    48 MHz (delta-sigma)

    Will a LMK04208 be able to do this?

    Thanks and regards,


  • Hi again Derek.

    One thing that's confusing me is the minimum output frequency in the parametric table on your website - it shows 0.305 MHz and 0.329 MHz for the LMK04832 and LMK04208 respectively. I would have rejected these devices as not capable of generating 40 kHz from 10 kHz in (the absolute minimum spec I need).

    Am I reading the tables incorrectly?



  • Hi Steve,

    Given the new frequency range also includes 10kHz, it becomes quite challenging to get every frequency you want. I don't think LMK04208 can do what you want. Explanation and additional guidance below.

    From the initial guidance, it seemed that LMK04832 or LMK04208 could be used to generate the required frequencies. The parametrics in the datasheet are likely trying to give a minimum output frequency in dual-loop mode, where the integrated VCO is used; even then I would expect LMK04832 to be closer to 0.24kHz based on the VCO ranges... Regardless, this is not an actual limitation of the output structure. The outputs on the LMK04832 or the LMK04208, especially in LVCMOS mode, can go as low frequency as needed. 

    However, the limitation is now that 48MHz and 10kHz are coming from the same device, implying a need for at least divide-by-4800. There is no mechanism to create a divide-by-4800 on the LMK04208 which would allow both 48MHz and 10kHz to be generated on the same device. 

    LMK04832 has a 13-bit SYSREF divider (8192), so if the VCXO frequency is changed to 48MHz this scheme would still work for LMK04832. Conveniently, the SYSREF divider can be run in continuous mode just like a regular divider, and also has a buffer which duplicates the SYSREF frequency to the feedback mux for use as PLL1 feedback. The remaining 10-bit dividers (1024) are sufficient to generate 1MHz, 120kHz, and 80kHz, with an additional divide-by-1 used for 48MHz.

    I've also attached a TICS Pro configuration showing how this would be done in LMK04832.

    LMK04832 config.tcs

    The LMK04832 solution would likely stand up to some additional frequency plan changes over time, although for some of the lower frequency divides e.g. 40kHz it may become necessary to add one or more D flip-flops on the output to expand the divide ratio slightly. Additionally, there would be a short addendum to the programming sequence to make sure that the dividers are all synchronized. If the CPU interrupt clock needs to be continuously running, the timing of the SYNC sequence may be impacted; in practice, I don't expect that getting the synchronization sequence correct is going to be challenging, especially if the clocks are allowed to be initialized at startup before anything depends on their output.

    One other consideration: 48MHz is not that common of a VCXO value, so distributors are unlikely to carry it for immediate ordering. You might need to talk to a VCXO vendor to get samples for quick testing. I think there are a few programmable VCXOs from SiTime which could be ordered immediately and programmed separately. Regardless, the sourcing strategy for the VCXO is probably the most difficult aspect of this solution.

    LMK5C33216 would still be able to implement your frequency plan, but again that device is very overfeatured for what you need, and would require some conversion to LVCMOS if the clocks cannot be provided as a different format. However, LMK5C33216 could generate essentially any of the low frequency clocks you require, regardless of how they change. In testing the output configuration tool in TICS Pro, I found that it was somewhat challenging to make the tool give me the requested configuration. I did eventually get a configuration which worked, but the tool appears to have some bugs that make configuring the device needlessly challenging. If you do want to test this device, just be prepared; the tool is in such a state that you will likely need some assistance from TI to generate the configurations once the frequency plan is known. I have taken note of the issues with the tool and we are working on a fix, but it will likely take a few weeks to deploy an updated version. You should still be able to program configurations (including any TI generates), it's just creating them in the tool yourself that's impacted.

    With LMK05318 and LMK01801, 48MHz and 10kHz could be generated on LMK05318; PLL1 could generate an output at e.g. 25MHz, which could be divided to 1MHz on one half of LMK01801; the other half of LMK01801 could divide 4.8MHz to 120kHz and 80kHz. All these signals could be LVCMOS except 48MHz, but 48MHz may be acceptable as a different format. All that said, based on your comments about potential changes to frequency, as the frequency plan evolves it may become difficult to make this solution work if the divider ratios stop being favorable. If flip-flops need to be added on the output of this solution, I think it loses a lot of benefits; the only remaining advantage would be using a DPLL to lock the reference, but unless you need the more complex features like holdover or DCO I'm not sure this is really an advantage.

    The most complex aspect of the LMK05318-based configuration, I think, will be controlling the precise phase alignment of all output clocks. They will be frequency-locked, but assuring that they are phase-locked may be a challenge given the spread across different devices and the lack of digital delay on the LMK05318 or 3/4 banks of the LMK01801.

    In summary: From an ease of use and rapid development standpoint, assuming you can get a 48MHz VCXO, I suspect it would be simplest to use LMK04832 in the configuration described above. It may actually be fastest to test on the LMK5C33216EVM, since no part changes would be required; however, I would not call this the simplest option.

    Hopefully this clears things up, and gives you some footing to make a decision.


    Derek Payne