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Original question:

DAC39J82: DAC39J82 and LMK04832 design review feedback

LMK04832: LMK04832NKDT

Arunkumar Palanisamy
Prodigy 160 points
Part Number: LMK04832

Hi,

We have used LMK04832NKDT for generation of JESD204B clocks and sampling clocks  for 3 DAC's.
The schematic section has been attached, please provide review feedback for the design. I have even attached the DAC Section Forum link for reference.

Design use details:

  1. All DACCLKP/N - AC coupled, LVPECL, 2520MHz
  2. All SYSREFP/N - Set as per lane rate and system clock frequencies, AC coupled option for DC coupling, LVPECL(AC coupled) LCPECL (DC coupled), <20MHz
  3. LMK Clock In 1 - 360MHz

 DAC Section Forum link :  e2e.ti.co[View:~/.../dac39j82-dac39j82-and-lmk04832-design-review-feedback

  • 0
    Prodigy 160 points

    0777.WTG_LMK04832_TI_Review.pdf

    Hi,

    I Have attached the LMK ClK Schematic section pdf.

  • +1 in reply to Arunkumar Palanisamy
    TI__Mastermind 28960 points

    Hi Arunkumar,

    Apologies for the delay... we had some E2E backend updates that mixed up assignments.

    • Are TEST_LMKCLK and MGTREFCLK0_223 at the same frequency as LMK_DACCLK3? If the frequencies can differ, you may want to swap the LMK_DACCLK3 net with some other clock group to reduce spurious coupling.
    • MGTREFCLK0_22x and PL_LMK_DEVCLK + PL_LMK_SYSREF are AC-coupled, is this LVDS? If so it should be fine.
    • CLKOUT0 termination looks okay to me
    • Loop filter, stability, etc looks okay to me
    • Power supply looks good to me
    • I see a bidirectional buffer for the CLKIN_SEL pins and the STATUS_LDx pins... but the same is not present on SPI, SYNC, RESET. Is this intentional? May want to double-check if a level-shifter is required for SPI bus and RESET/SYNC.

    Regards,

    Derek Payne