CDCE925 data sheet mentions below points:
a) On-Chip VCXO: Pull Range ±150 ppm : Is this means the input clock source can have a tolerance up to ±150 ppm? Question especially applies when using a 16Mhz oscillator as input source.
b) Enables 0-PPM Clock Generation : Request to elaborate this concept. Even if the input clock source has tolerance up to ±150 ppm will the output can be generated with 0ppm tolerance?
We are designing a clock architecture using CDCE925 with input clock source from a 16MHz oscillator and the oscillator has a 50ppm tolerance. But the devices connected to the output of CDCE925 requires a tolerance of less than 30ppm. Will this can be achieved by CDCE925 (higher input tolerance and lesser output tolerance) ?
Regards,
Thomas CN