This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMX2594EVM: LMX2594 Channel Divided 48 OUTB not good

Part Number: LMX2594EVM
Other Parts Discussed in Thread: LMX2594,

Hi team

I am using LMX2594 for making one 75000MHz Clock(RFOUTA) for DAC and one 156.25MHz clock(RFOUTB) for FPGA JESD204B IP Core。I test the clock on LMX2594EVM first

The TICS Pro set is as follows:

Very simple,no using sync and SYSREF functions. but the actually 156.25Mhz output clock has very large spur. and the time domain scope image is not like a clock signal。

But the PLL set didn't violate rules in datasheet. I want to have some debug advise

 

  • Update some information:

    the 75000Mhz signal is just right,but the 156.25Mhz signal is very bad, almost can't use. I try to upload the scope image,but can't load successfully ,I don't know why

  • Hi Wenc,

    the 156.25MHz clock is a square wave clock, there will be a lots of harmonics.

    When you use a scope to measure this signal, please make the scope impedance to 50Ω. If you only measure one of the output pins, terminate the other pin to a 50Ω load.