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LMX2592EVM: LMX2592EVM will not operate with input higher than 600 MHz

Part Number: LMX2592EVM
Other Parts Discussed in Thread: LMX2592, LMX2594

I am evaluating the LMX2592-EVM. It operates well with input frequencies up to about 600 MHz. Beyond that, I am unable to get the board to function. Interestingly, the board will not function with an 800 MHz reference input but if I change the input to 400 MHz and engage the doubler such that the chip sees 800 MHz internally, I get good results. The instructions for the EVM board say to apply 100 MHz and doesn't mention going higher than that. The data sheet specifies operation from 5 MHz to 1400 MHz for the chip itself. Is there a problem with the board that is crippling high frequency inputs?

  • Hi Brian,

    While the LMX2592 can operate with up to 1400MHz reference input, subsequent blocks may not work correctly unless the reference frequency is divided down in the Pre-R stage. I believe the maximum supported frequency into the PLL_R divider is 250MHz, based on similar restrictions in LMX2594 (with a similar input stage). Try using the Pre-R divider to reduce the input frequency to <250MHz before it hits the R divider.

    I believe we did not capture this limitation anywhere in the datasheet or the GUI. I'll make a note to clarify this limit (whatever it may be) in a future release of both.


    Derek Payne

  • Hi Derek,

    Thanks for the very logical reply. I did already try this though. With an 800 MHz input I tried setting the first R divider to "8" and the second to "1" with no results. Also tried "4" and "2" with equally disappointing lack of operation. Strangely, the board works with a 400 MHz input and the doubler turned on followed by a divide by 8 then divide by 1 on the R dividers. The internal frequency would be 800 MHz in this case of course. I am driving the reference port single ended with the other port terminated to 50 ohms. Increasing the reference drive level doesn't seem to help. I have it set to +10 dBm at the moment which works fine at lower frequencies. 


    Brian Walker

  • Hi Brian,

    What were the setting for FCAL_HPFD_ADJ and CAL_CLK_DIV? These registers should be set according to the fpd and OSCin frequency in order to produce a robust VCO calibration.

  • Hi Noel,

    Thanks for your suggestions. I had ACAL_CMP_DLY set to 100, FCAL_LPFD_ADJ set to Fpd >=10, FCAL_HPFD_ADJ set to Fpd <= 100, and the Fpd is set to 100 MHz. The VCO frequency is 4600 with Prescaler of 2 and N of 22 with Fnum/FDen equal to 1/1. Final output is /3, /8, /8 for a total of 192 and 23.958 MHz output.


  • Hi Brian,

    You should make CAL_CLK_DIV = divide by 8 otherwise VCO calibration will fail.

    Your N-divider value is not correct, this is an integer channel, NUM should be 0.

    Please try below configuration.

  • Thanks!! This works well. I'll have to read more about the limits of some of the settings.