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LMX2581E: How does microwire readback work?

Part Number: LMX2581E

I'm confused by 8.13.14.2 (serial microwire readback).

It appears as though LD or MUXOUT are constantly being driven with readback data (regardless of LE). Is this the case?

So, if I program MUXOUT_SELECT to be READBACK, the MUXOUT line will just repeatedly send the value of RDADDR on every CLK tick?

If all of that is true, the MUXOUT cannot be shared with other devices (like a MISO line in SPI) unless I perform a sequence of 4 writes:

  1. Write R7 to take MUXOUT into push/pull mode
  2. Write R6 to pick the register to readback
  3. Write R6 again (i.e. with asserted LE as per Figure 18) but reading the output bits
  4. Write R7 to put MUXOUT into tri-state mode

Even then, it's not clear MUXOUT will have the correct phase. (i.e. if another device on the SPI bus uses 12 CLKs for a read/write cycle, and the CLK is shared with the LMX2581E, it's now 20 CLK cycles out of phase with the SPI master) Am I understanding that correctly?

Even if I dedicate MUXOUT to this device and use an external switch for MISO, reading back a register requires both steps 2 and 3 above, correct?

Thanks for the help!

  • Mike,

    You understand correctly: if MUXOUT is configured for microwire readback, register data in RDADDR data will constantly be generated at the MUXOUT pin during every microwire transaction unless MUXOUT_PINMODE is configured to tri-state. I believe, but cannot confirm until tomorrow, that toggling LE low->high resets the readback circuit so that there would be no phase misalignment issues; I will get back to you with my findings.

    Readback for all but the special readback codes defined in table 10 requires steps 2/3 as you have surmised. If ID=1, the readback value is pin-programmed.

    Regards,

    Derek Payne

  • Thanks so much! Confirmation that the LE will reset the readback circuit resolves the only remaining question. If that's the case, I can safely share CLK and MOSI with other devices, use a standard SPI CS for LE, but just need to be careful with MISO/LD/MUXOUT.

  • Mike,

    This device is just old enough that we're having a little trouble getting into the design database for it to confirm the MUXOUT behavior. I'd love to just test it myself on the bench, but we don't have that board in the lab and it'll take longer to arrive than to wait for design db access. Sorry for the delay... I'll keep you posted.

    Regards,

    Derek Payne

  • Thanks for looking into it!

  • Got an answer!

    Toggling LE high->low OR low->high resets the readback circuit and the next 28 clock cycles will shift out data. After a LE transition in either direction and subsequent 28 clock pulses, MUXOUT will output 1. This means you could put configure MUXOUT as open-drain and safely interact with other SPI devices on the same bus, assuming those devices can go tri-state or high-impedance while not selected.

    It seems that if you want to write to the microwire bus, and then readback from a different device, you should perform the write, bring LE high, and either generate an additional >29 clock pulses to force readback to 1 in open-drain mode, or use some external MUXOUT buffer with an active-low enable tied to LE to block the inevitable data readback + MUXOUT=1 condition in push-pull mode.

    Regards,

    Derek Payne

  • You're awesome, Derek. Thanks!