I'm confused by 8.13.14.2 (serial microwire readback).
It appears as though LD or MUXOUT are constantly being driven with readback data (regardless of LE). Is this the case?
So, if I program MUXOUT_SELECT to be READBACK, the MUXOUT line will just repeatedly send the value of RDADDR on every CLK tick?
If all of that is true, the MUXOUT cannot be shared with other devices (like a MISO line in SPI) unless I perform a sequence of 4 writes:
- Write R7 to take MUXOUT into push/pull mode
- Write R6 to pick the register to readback
- Write R6 again (i.e. with asserted LE as per Figure 18) but reading the output bits
- Write R7 to put MUXOUT into tri-state mode
Even then, it's not clear MUXOUT will have the correct phase. (i.e. if another device on the SPI bus uses 12 CLKs for a read/write cycle, and the CLK is shared with the LMX2581E, it's now 20 CLK cycles out of phase with the SPI master) Am I understanding that correctly?
Even if I dedicate MUXOUT to this device and use an external switch for MISO, reading back a register requires both steps 2 and 3 above, correct?
Thanks for the help!