Can you please help answer my customer's question:
I have a LMK03318RHS in a design with another TI part, and the other part’s datasheet states that its clock inputs must remain tri-stated while its power supplies are off. The inputs to the part receiving the clocks are LVDS, so I intend to have the outputs of the LMK03318RHS set for LVDS mode, but disabled as the receiving part is being powered up, and then the clock outputs of the LMK03318RHS will be enabled after power to the receiver is up and stable. I believe that the LMK03318RHS supports this operation, namely that the output channels of the device can be individually controlled, and while configured as LVDS can be tri-stated, but I want to make sure that I am reading the datasheet of the LMK03318RHS correctly.
I believe the operation is controlled by LMK03318RHS ‘OUTCTL_0 Register; R31’ for output 0 for example, is this correct, and is the part able to have its output tri-stated in LVDS mode. So can the LMK03318RHS be controlled as I described, and are the individual channels truly tri-stated while disabled and in LVDS mode?