LMK00101: questions

Adam,

• With only two inputs and four outputs, LMK00105 (2 input, 5 output) is probably the better choice - note that the OSCin interface can be driven as a single-ended LVCMOS input (see Figure 8 in LMK00105 datasheet or Figure 11 in LMK00101 datasheet). For either device, unused inputs and outputs should be left floating - inputs can be left floating per guidance given in Table 2 and Table 3, and outputs can be left floating per datasheet guidance on using less than all outputs.
• We don't have this specific data. But judging by the plots in Figure 2 and Figure 3 of the datasheet, it should be clear that there will be significant increases in the noise floor - just by linear extrapolation from the last data point it looks like several hundred femtoseconds of additive jitter. I would not recommend operating the device with less than 2V/ns input slew rate.
• The input bias voltage for the OSCin pin is nominally VDD/2. This can be inferred from Figure 8 (LMK00105) or Figure 11 (LMK00101) AC-coupling the external LVCMOS driver to the OSCin pin.
• Both OSCin and CLKinX pins can be driven with a single-ended sine wave, provided they meet the single-ended input specifications listed in the electrical characteristics. OSCin doesn't list input specifications, but will have comparable signal swing requirements to the CLKin inputs.
  
  Note that the biggest problem with using a sine wave will be the limited slew rate; as discussed above you ideally need 2V/ns or greater to get decent additive jitter performance. For single-ended sine waves the slew rate depends on frequency: SR = 2π*f*Vpk. Maximum single-ended swing is specified as 2Vpp, so Vpk = 1V at best; this implies that to get 2V/ns slew rate, the frequency must be > (2V/ns) / (2π*1V) > 318MHz, which exceeds the maximum operating frequency range of the OSCin pin. You may have better luck driving a balun to get a differential sine wave, since this increases the slew rate by a multiple of sqrt(2), reducing the maximum permissible frequency to (2V/ns) / (2π*sqrt(2) * 1V) = about 225MHz without any additional amplification; if you increase power by a further 3dB at the input, you get another sqrt(2) amplitude improvement and now you can do about 159MHz at 2V/ns. In any case, single-ended sine wave is clearly a challenge for achieving the necessary slew rate at much lower frequencies.
  
  I'll also point out the LMK00804B has an LVCMOS input and a differential input, and shows a similar trend with additive jitter and noise floor vs input slew rate. You need a high-frequency and high power sine wave, or you need a clipped sine wave with higher slew rate than the power suggests, or you need a sine-to-square-wave converter that preserves the close-in noise performance (for example take a look at this link section 3.4.1.1 for discussion of sine-to-square techniques used in a 10MHz rubidium oscillator), possibly followed by a jitter-cleaning PLL that can generate an output with high slew rate at the lower frequency for much lower noise floor than a logic device can provide (though in the link above there is some data at 100kHz to suggest this may not be necessary). Low-noise sine-to-square conversion at low frequency is a hard problem, and our LVCMOS buffer will not solve it for you.

Regards,

Derek Payne