Hello,
The CDCE925 data sheet Pin Functions table mentions the Xin/CLK and S0 pins as LVCMOS compatible input pins. Normally LVCMOS logic levels are referenced to 3.3V.
But the recommended operating conditions table mentions the input voltage for CLK and S0 pins as 1.9V maximum.
Please clarify the below questions:
1) Whether the CLK and S0 input pins of CDCE925 can accept 3.3V input signals?
2) If the maximum input voltage is only 1.9V and not 3.3V, then how the pins are being LVCMOS pins?
Regards,
Thomas CN