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CDCE925: Xin/CLK: Vi @ 2.5V and 6 mA

Part Number: CDCE925
Other Parts Discussed in Thread: CDCE913

Dear Sirs,

regarding the CDCE913 CLK in voltage range, for which we wrongly assumed it is 3.3v compatible, as described in this topic:

    https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1075713/cdce925-clk-and-s0-pins-3-3v-compatibility?tisearch=e2e-quicksearch&keymatch=cdce913%20clk%20voltage

our question is, will designs which are "forced" 3.3v over serial resistance and yield 6 mA of input current to the CLKin pin which settles at about 2.5 V, fail with time?

Now after finding this we have checked the Vdd voltage 1.8 V and is stable, as consumption of Vdd as per specs is said to be ~9 mA per PLL. Jitter from this CDCE is also as per specs.

Of course we will correct this with a proper divider (series at source, and parallel at destination) termination, to balance the line.

Kind regards,
Uros