Other Parts Discussed in Thread: CDCE913
Dear Sirs,
regarding the CDCE913 CLK in voltage range, for which we wrongly assumed it is 3.3v compatible, as described in this topic:
our question is, will designs which are "forced" 3.3v over serial resistance and yield 6 mA of input current to the CLKin pin which settles at about 2.5 V, fail with time?
Now after finding this we have checked the Vdd voltage 1.8 V and is stable, as consumption of Vdd as per specs is said to be ~9 mA per PLL. Jitter from this CDCE is also as per specs.
Of course we will correct this with a proper divider (series at source, and parallel at destination) termination, to balance the line.
Kind regards,
Uros