Other Parts Discussed in Thread: LMX2594
When using the LMX2820 in integer N mode, should the MASH_RESET_N bit in Register 35 be set to 0?
On a related chip like the LMX2594, the MASH_RESET_N is set to 0 for Int-N and set to 1 for Frac-N mode. Does the same apply for the LMX2820?
Is there some internal PN generator (spur source) or circuitry that is disabled when MASH_RESET_N is set to 0?
Thanks
K