Hi,
We are using this part for LVCMOS Input and LVCMOS output function where the output of Y1 is used. The Differential LVPECL output on Y0 / Y0_N is left floating. To disable the LVPECL function, we intend to GND pins VDD0 &VDD0_1 (Pins 9 and 12). Pins 10 and 11 are left floating. Is that fine to proceed accordingly?
The DS comment says VDD0 and VDD0_1 can be pulled to GND. Is it fine to supply VDDPECL supply when LVPECL is not used in our functionality?
As for the single ended input the AC coupled LVCMOS input is fed to IN (Pin 2) and the IN_N (Pin 3) is tied to VBB(Pin 4).
The schematic we have is as follows
Pls confirm.
