LMK5C33216: How to realize the hitless switching in LMK5C33216

Hi Zhizhao,

Zhizhao Niu said:

1. Does the hitless switching function is unique for DPLL only? I found in APLL jitter cleaner, such as LMK04906, it also have the hitless switching and phase cancellation. So I want to know if they are same or not? 

The LMK04906 does have a hitless switching behavior, but wouldn't meet G.8262 switching requirements.  The DPLL does a much better job resulting in hitless switching.  Please refer to the G.8262 compliance test result for details.

Bottom line, with the LMK5C33216 when the reference is lost, the DPLL will stop updating the APLL numerator (which it was doing to keep it phase and frequency locked to the reference).  This means your long term holdover stability will be linked with the performance of the XO, TCXO, or OCXO that you use as XO input.  Holdover accuracy relates to PLL numerator being set to a single value.  The resolution is generally < 1 ppt.  This relates to the 40 bit APLL denominator and phase detector frequency.

On LMK04906 when the reference is lost it will force the voltage onto the Vtune of the VCXO.  The worst case frequency accuracy during holdover relates to the Kvco of the VCXO and the voltage tuning step size 3.3 V / 1024.  This will often result in holdover frequency accuracy on the order of 2 to 16 ppm depending on the Kvco of the VCXO.

Zhizhao Niu said:

2. What is the background principal of phase cancellation and slew rate control? 

When exiting holdover, the DPLL will measure the phase of the new reference compared to the current holdover frequency/phase.  Then once measured it is able to exit holdover with that phase offset as the difference between reference and feedback.  This allows you to exit with very little frequency/phase hit.

If desired, it is possible for the DPLL to drive the input to feedback phase error back to 0 at the rate defined by thres and timer values.

Zhizhao Niu said:

3. How to set the DPLLx_PHS1_THRESH and DPLLx_PHS1_TIMER register value? Can I calculate it as Maximum phase error=1/Fpfd=DPLLx_PHS1_THRESH*DPLLx_PHS1_TIMER? 

Off hand I don't recall the exact equation.  I think the TICS Pro software may calculate this for you based on your inputs.  I can confirm and update you.

Can you elaborate more on what you mean by maximum phase error and where and when you want to measure the maximum phase error?  For example, maximum phase error could be the worst case phase of the input vs. the feedback after being divided down to the TDC frequency... so the worst case in that sense would be half the period of the TDC.

73,
Timothy