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LMK04828: Which clock scheme would be better to realize the lower phase noise DEVCLK generation and multichannel clock solution with phase alignment?

shen jie
Prodigy 185 points
Part Number: LMK04828
Other Parts Discussed in Thread: TIDA-01021, LMX2594, , LMK00804B, LMK61E2

Hi, 

I would like to use LMK04828B+LMK2594 to provide device clock(10GHz) and sysref(4.8828125Mhz) clock to 4pcs ADC at the same time,  and realize multichannel clock solution with phase alignment. 

It is important that  4pc ADC sample synchronously, so clock scheme should be selected to minimize the sampling skew. I  plan to use JESD204B subclass1 to realize multi-chip synchronization,

As below figure shown, which clock scheme would be better to realize the  lower phase noise DEVCLK generation and multichannel clock solution with phase alignment? Option1 or Option2?

 Thanks in advance!

Option1:

Option2: refer to design of TIDA-01021 partially

  • 0
    TI__Genius 12550 points

    Hi,

    In the option 1, reference input to LMX2594 include the PLL noise of the LMK04828, whereas options 2 has OSCout noise floor only. 

    On the phase noise performance using the OSCout, you can see the section 4.2.1 in TIDA-01021 design guide and it adds very minimal noise to reference input.  

    Regarding the option 1, I would be suggesting to use the PLLatinum sim tool to simulate and see the CLKout performance of LMK and overall performance of LMX output. 

    Now, regarding the multi-clock sync, SYNC input to LMX will be critical to synchronize SYSREF outputs and should be recommend to have precise aligned to all LMX devices.

    Thanks!

    Regards,

    Ajeet Pal 

  • 0 in reply to Ajeet Pal
    Prodigy 185 points

    Hi,

    Your meaning that using the OSCout in Option2  have been verified in TIDA-01021, so it is better than the Option1 at the phase noise point of view , am I right?

    Regarding the multi-clock sync, I only match the PCB length of SYNC input to all LMX2594 from 1to4 buffer as marked blue arrow in the below figure, am I right?

    Wait for your response!

    Thank you very much!

    Best regards!

    Jason

  • 0 in reply to shen jie
    TI__Genius 12550 points

    Hi Jason,

    shen jie said:
    Your meaning that using the OSCout in Option2  have been verified in TIDA-01021, so it is better than the Option1 at the phase noise point of view , am I right?

    I apologies, but not sure the phase noise comparison in TIDA-01021 done with OSCout or direct reference input. If you interested, I could performed the test and will provide the data. It may need some time. But overall understanding is OSCout have better phase noise compared to DCLK.

    shen jie said:

    Regarding the multi-clock sync, I only match the PCB length of SYNC input to all LMX2594 from 1to4 buffer as marked blue arrow in the below figure, am I right?

    SYNC inputs should be aligned to each other as well as to meet the setup and hold timing requirement for LMX2594 to synchronize them. Apart from SYNC input, OSCin of the LMX2594 should be aligned as output will aligning with OSCin after sync and if there is delay on OSCin, it may reflect at output also.

    Thanks!

    Regards,

    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Prodigy 185 points

    Hi, 

    If you have time for test, I will appreciate you very much!

    So, I must match PCB length for 6 Group firstly. Then, setup and hold timing requirement of SYNC( aimed at OSCin clock) for LMX2594 could be adjusted through applying digital or analog delay of SDCLKout3 as below figure shown, am I right? 

    After all OSCout mode from LMK04828B don't have delay circuit in the chain, which only buffer clock input from OSCin

    Also I have other two questions about user-guide of TIDA-01021:

    1. I don't understand how to exchange the the positive and negative signals of the differential pair?

    That means to toggle SYSREF_GBL_PD to 1 and SDCLKoutY_DIS_MODE to 0x01 which make SDCLKout pins conditionally low firstly, then toggle SDCLKouY_POL to change the polarity?

    2.  This 0-delay PLL mode is the Cascaded Zero-Delay mode? The source of feedback is the SYSREF Divider?

    Many thanks to you again!!!

    Best regards!

    Jason

  • 0 in reply to shen jie
    TI__Genius 12550 points

    Hi Jason,

    shen jie said:
    If you have time for test, I will appreciate you very much!

    It may take sometime and can update you by next week.

    shen jie said:

    So, I must match PCB length for 6 Group firstly. Then, setup and hold timing requirement of SYNC( aimed at OSCin clock) for LMX2594 could be adjusted through applying digital or analog delay of SDCLKout3 as below figure shown, am I right? 

    After all OSCout mode from LMK04828B don't have delay circuit in the chain, which only buffer clock input from OSCin

    To meet the setup and hold time of LMX2594 SYNC input, SDCLKout3 can be adjusted but if there is an delay between SYNC after buffer, then there can be possibility to have delay between the output. There won't be any scope to adjust the individual SYNC input.

    shen jie said:

    1. I don't understand how to exchange the the positive and negative signals of the differential pair?

    That means to toggle SYSREF_GBL_PD to 1 and SDCLKoutY_DIS_MODE to 0x01 which make SDCLKout pins conditionally low firstly, then toggle SDCLKouY_POL to change the polarity?

    That was needed to have SYSREFREQ input of LMX2594 to keep high to generate SYSREF in generation mode. This input can be avoided by keeping the pull up option at SYSREFREQ input. I would be suggesting to have the input option and keep pull up input to have all possible inputs at SYSREFREQ input.

    shen jie said:

    2.  This 0-delay PLL mode is the Cascaded Zero-Delay mode? The source of feedback is the SYSREF Divider?

    If operating in dual PLL mode, it should be in 0-delay nested dual PLL mode, where SYSREF feedback should be at PLL1 loopback.

    Thanks!

    Regards,

    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Prodigy 185 points

    Hi,

    If each LMX2594 need two SDCLKout from LMK04828B as SYNC and SYSREF , 4pcs LMX2594 need 8 SDCLKout. But LMK04828B have only 7 SDCLKout at most, so I only use 1 to 4 buffer to drive SYNC in option2.

    Suddenly I have another option3 as below figure.1 shown: exchange SYNC and SYSREF of LMX2594, and let SYSREF use 1 to 4 buffer. It will make the each SYNC have adjustable delay. At the same time, pull up SYSREF input as your suggestion:

    When the LMK2594 work on master and non pulse mode, I will disconnect SYSREF from 1to 4buffer by removing the serial resistor and let pull up take effect

    when the LMK2594 work on master and pulse mode, I will keep connection SYSREF with 1 to 4buffer and let LMK04828B produce a pulse to trigger LMX2594.  

    when the LMK2594 work on repeater mode, I will keep connection SYSREF with 1 to 4buffer too and let LMK04828B produce continue clock to trigger LMX2594.  

    How do you think about option3 compared to option2 at the low phase noise and low channel to channel skew point of view?

    By the way, the 1to4buffer(LMK00804B) have very low output skew about <35ps as below figure.2 shown.

    figure.1 option3 

    figure.2 output skew of 1 to 4 buffer 

    Thank you very much!

    Best regards!

    Jason

  • 0 in reply to shen jie
    TI__Genius 12550 points

    Hi Jason,

    Option 3 seems to have more flexibility to have different type of SYSREFs and sync options.

    I think, you should go ahead with option3, which can have better options for low skew and phase noise.

    I'll try to provide the LMX2594 performance data with OSCout option.

    Thanks!

    Regards,

    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Prodigy 185 points

    Hi,

    Now it is clear for me so much. Thank for your patience to answer my so many questions, I will be waiting for your test result:) 

    Now, there is a last question about ZDM: 

    In the Clock or channel skew test of TIDA-01021, LMK04828 is configured in 0-delay SYSREF mode. On the last post you said  "If operating in dual PLL mode, it should be in 0-delay nested dual PLL mode, where SYSREF feedback should be at PLL1 loopback".  In fact LMK61E2 provide the reference clock into the OSCin of LMK04828, then LMK04828 buffer  this clock out to LMX2594 through OSCout pin. So I think it should work on single PLL mode, am I right? 

    Also single PLL mode only use Cascaded zero-delay?

    0-delay SYSREF mode means that FB mux select feedback from SYSREF Div?

    Many thanks to you！！！

    Best regards!

    Jason

  • 0 in reply to shen jie
    TI__Genius 12550 points

    Hi Jason,

    Yes, 0-delay mode can be operated in single PLL, dual PLL configuration mentioned in section 9.4.3 and 9.4.4 in LMK04828 datasheet. In TIDA-01021 reference design, LMK04828 operated in 0-delay single PLL mode (PLL2) and powerdown the PLL1.

    shen jie said:
    Also single PLL mode only use Cascaded zero-delay?

    Single PLL mode used only PLL2, it power down PLL1 section. Input to PLL only at OSCin input.

    shen jie said:
    0-delay SYSREF mode means that FB mux select feedback from SYSREF Div?

    That's true.

    Thanks!

    Regards,

    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Prodigy 185 points

    Hi, Pal:

    I have a question about output format of SYNC out from LMK04828B to LMX2594 on the Xilinx clock demo board as below figure 1 shown.

    Is this format is OK for LMX2594? It seems that this format is not in line with the format suggested in the datasheet shown in the Figure 2.

    The TIDA-01021 use Balun to change Differential to single(CMOS) in the below Figure 3, so it is not a problem.

    Figure 1. output format in the Xilinx demo board

     

    Figure 2

    Figure 3. TIDA-01021

    Thank you very much!

    Best regards!

    Jason

  • 0 in reply to shen jie
    TI__Genius 12550 points

    Hi Jason,

    The SYNC input termination in Xilinx clock board doesn't seems to be good and need to provide in as suggested in Figure 31 in datasheet or can provide differential to single ended conversion mentioned in TIDA-01021 board.

    The below thread may help you to setting the SYNC input for LVDS format.

    (+) LMX2594: LVDS SYNC input spec, termination and register setting - Clock & timing forum - Clock & timing - TI E2E support forums

    Thanks!

    Regards,

    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Prodigy 185 points

    Hi, Pal:

    Thank for your response in time!  The thread post by you is very helpful:)

    For LMK04828B,  typical VOD of LVDS  shown in the below Figure 1 is 395mv， so Vpp will be 790mV. That means it will meet requirement of "LVDS works to 250 mVPP"  or ">=250 mVpp" ?

    Please check my schematic in the figure2,  and is it will meet the requirement of figure 3?

    I don't like using differential to single ended conversion  because there are multiple conversions needed in my design. it will bring some part to part skew.

    Figure 1

    Figure 2

    Figure 3

    Thank you very much!

    Best regards!

    Jason

  • 0 in reply to shen jie
    TI__Genius 12550 points

    Hi Jason,

    Yes, LMK04828 LVDS output swing will support for LMX2594 SYNC input as LVDS input. 

    Schematic looks good and would be great to have R1201, R1172 and C1612 components very close to each other so it will not create any stub, when R1172 and C1612 are DNP.

    Thanks!

    Regards,

    Ajeet Pal