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LMK04828BEVM: Tracked CPout1 Holdover Mode test procedure

Part Number: LMK04828BEVM
Other Parts Discussed in Thread: LMK05318, LMK04832, LMK5B33216, LMK5C33216

Hello,

My customer will like to test the Tracked CPout1 Holdover Mode using the LMK04828BEVM.

Could you please provide the test procedure along with a sample setup file?

Thank you.

JH

  • Hi JH,

    All that should be required is setting: MAN_DAC_EN = 0 and TRACK_EN = 1, as per 9.3.7.1.2 Tracked CPout1 Holdover Mode.

    Now of note, once in holdover, the tracking can take you close in frequency to the reference.  To exit holdover, the phases of reference input and holdover clock need to align.  This means if the phase is not close to 0, because frequency is so close, it can take a while to drift into phase - I don't know if you have timing requirements to exit holdover?

    Note the LMK04832 has a feature which can help speed up this exit time.  The DPLL products such as LMK05318 and LMK5C33216, LMK5B33216 give the best holdover performance and entry/exit behavior.

    What kind of holdover specifications are needed?

    73,
    Timothy

  • Hi Timothy,

    Thanks for your help.

    I will test the Tracked CPout1 Holdover mode with the following procedure. Please review it.

        1. Load the following file (MAN_DAC_EN=0 and TRACK_EN = 1)

            LMK04828BEVM.tcs

        2. Check that both PLL1 and PLL2 are locked

        3. Shift the 30.72MHz reference clock frequency appropriately

        4. Read 0x188 to see if holdover mode is active

        5. Return the 30.72 MHz reference clock frequency to normal

        6. Read 0x188 to see if holdover mode is inactive

    Regards,

    JH

  • Hi JH,

    One thing I might add, you can readback the DAC value to see it track as you move the reference frequency around... this may be better than the holdover.

    Note, LMK04832 has a slightly nice interface for this... it will calculate the DAC update rate... this calculation should be the same between 4828 and 4832.  Although LMK04832 has some slightly different LOS features as I recall.

    73,
    Timothy

  • Hi Timothy,

    Thanks for your help.

    We confirmed that the Tracked CPout1 Holdover mode worked on the EVM.

    However, when the holdover mode was activated, the output frequency shifted from about 1.5KHz to 42KHz for each case. Is this a normal characteristic of holdover mode?

    Is it possible to output the same frequency as the normally locked output frequency through the Tracked CPout1 Holdover mode?

    Regards,

    JH

  • Hi JH,

    When entering holdover, the accuracy will be with-in +/-2 * 3.2 mV * Kvco.  Now this frequency will be PLL1 frequency which translates to output through PLL2 and then output dividers... so I cannot comment without knowing more info if this is the expected.  To get the +/-2 LSB yu need to ensure you are not running the update loop too fast.

    73,
    Timothy

  • Hi Timothy,

    When in tracked CPout1 mode, is there a minimum waiting time for the PLL1 tuning voltage to be acquired to enable stable holdover mode?

    How do I know if the LMK0482x is ready for stable traced CPout1 holdover mode activation?

       To get the +/-2 LSB yu need to ensure you are not running the update loop too fast.

    Thanks,

    JH

  • Hi JH,

    As far as "too fast" --> from datasheet section 9.3.7.1.2...

    When the DAC has acquired the current CPout1 voltage, the DAC_Locked signal is set, which may be observed on Status_LD1 or Status_LD2 pins by programming PLL1_LD_MUX or PLL2_LD_MUX, respectively.

    and

    Tracked CPout1 Holdover ModeThe DAC update rate should be programmed for 100 kHz to ensure DAC holdover accuracy.

    73,
    Timothy