LMK04832: Unsure of Validity of Clock Outputs

Cameron,

A quick primer on the differences between dual-loop (PLL1 + PLL2 cascaded), single-loop (PLL2-only), and distribution mode:

• Dual-loop utilizes both PLLs, with PLL1 at a low bandwidth and PLL2 at a higher bandwidth. PLL1 acts as a "jitter cleaner" in the sense that it has a low bandwidth and a relatively clean VCXO that rolls off reference noise very effectively even for high-noise reference inputs. Since PLL1 is low bandwidth, there is rarely a large penalty for reducing the phase detector frequency, so PLL1 can also be used to translate frequencies to domains with very low GCD (such as 100MHz and 122.88MHz, which only share a GCD of 160kHz). PLL2 acts as a frequency multiplier with a high bandwidth, since the reference to PLL2 is a clean VCXO signal and there are phase noise advantages to running the phase detector frequency and loop bandwidth much higher than PLL1. PLL2 is used to generate an LCM frequency, or a multiple of the LCM frequency, so that all other clocks can be divided down.
• Single-loop utilizes PLL2 exclusively. As long as the reference input is already clean on arrival, PLL2 can behave exactly like it does in the dual-loop configuration. 
• Distribution mode bypasses all the PLLs and directly passes the output to the clock distribution path, instead of using a higher-frequency VCO output. This is conceptually straightforward, but there are some drawbacks (the resolution of digital delay is based on the period of the clock distribution frequency, so step size will be smaller in a PLL mode than in distribution mode unless the distribution input is very high frequency; SYSREF divider minimum divide value is 8, which imposes restrictions on the usable reference input frequency).

We can try both the PLL2-only and distribution mode configurations (since you don't have a suitable VCXO frequency for the 100MHz, 50MHz, and 6.25MHz clocks to be derived from PLL2 with a high phase detector rate, running in dual-loop mode is not a great idea).

For PLL2-only mode, I click Set Single Loop in the Set Modes page of TICS Pro. I configure CLKin1 as the input reference (CLKin1_DEMUX set to PLL1, CLKin_SEL_MANUAL set to CLKin1 Manual, PLL2_RCLK_MUX set to PLL1 CLKinX) and power down OSCin (OSCin_PD = 1). Since I happen to know that VCO0 has slightly better phase noise than VCO1, and all your frequencies can be derived from PLL2 VCO of 2500MHz, I can set VCO_MUX to VCO0 and set the N-divider and N-prescaler to 5 and 5 respectively. I also set the N cal divider alongside the N-divider, for reasons that are explained in greater detail in the datasheet (look for VCO calibration) but which are unimportant right now. I then configure the output dividers and SYSREF as needed to produce the configuration below. Note that it doesn't seem possible to use a 6.25MHz SYSREF from the SYSREF divider alongside a 100MHz CMOS SYSREF, since the whole point of SYSREF in JESD204B is that it's the GCD frequency (or an integer divisor thereof) of all clocks in the data converter system - I selected this to be 100MHz continuous from device clock instead of SYSREF. Also note that when using an odd divider value, the duty cycle correction bit (DCLKx_y_DCC) must be set to 1 to achieve proper 50% duty cycle.

PLL2-only.tcs

For distribution mode, I click Set Distribution in the Set Modes page of TICS Pro. This powers down all the PLL components for me. I set the SYSREF divider to 16 instead of 400 since my clock distribution is now at 100MHz. All 100MHz clocks are configured with DCC + HS set, since this is required for divide-by-1.

distribution.tcs

For now, synchronization and getting phase alignment between all the outputs is going to be left as an exercise for the reader (see section 8.3.4.1 in the datasheet). There is a step-by-step example of getting phase alignment offered in the datasheet.

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Regarding highlighting, the state of the LMK04832 GUI is pretty abysmal. I've been looking for a good justification to take the time to polish it for a while, and now seems as good a time as any... an improved version should be available either later this week or sometime next week.

Regards,

Derek Payne

Awesome, thank you so much for the in depth response/education as well as the attached TICS files! I really appreciate the help, I was feeling rather lost in what settings to use. Haha sounds good, I'll keep an eye out for that.