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LMK04832-SP: Using LMK04832 LVDS Output as Input to SYSREF on AFE7950

Jack Zhang
Intellectual 480 points
Part Number: LMK04832-SP
Other Parts Discussed in Thread: AFE7950, LMK04832, AFE7950EVM, LMK04828

Hello TI e2e, I was hoping to get some design recommendations for a design involving the TI LMK04832 and AFE7950 parts. The design involves generating a 3.90625 MHz LVDS clock from the LMK, which feed into the SYSREF inputs on the AFE. I would be using one of the odd CLKOUTX pairs on the LMK. My question involves LVDS common mode biasing, because according to your AFE79XX_schematic_layout_checklist on the secure site, the SYSREF needs to be set externally to 0.6 V, which is the min Vcm on the AFE datasheet, pg 19 (snippet below) and the max Vcm being 0.8 V. The typically VOD swing is 0.75 Vpp.

I was provisioning for 0.1 uF AC coupling on each SYSREF +/- line, which would remove DC offsets and alter the common mode voltage level, but this may not be optimal for what the AFE SYSREF input is expecting, and I'm sure about the its biasing capabilities. Could any suggestions be offered for setting the common mode externally? Perhaps I would need a resistor network to DC return current paths? Thanks for your time. 

  • 0
    TI__Genius 12550 points

    Hi,

    LMK04832 LVDS output format can have higher CM voltage and would be good swing for AFE7950.

    If you want to have AC coupled SYSREF input from LMK04832, the LVDS swing would be ok and can keep external DC biasing voltage at AFE7950 SYSREF inputs.

    Else, can have DC coupled input from LMK04832 in LVDS format and provide resistive network mentioned in AFE7950EVM. It would keep CM voltage in the range of AFE expected DC voltage range along with needed voltage swing range.

    Thanks!

    Regards,

    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Intellectual 480 points

    Thanks for the reply, Ajeet. Do you have recommendations on the optimal implementation? From your response, it seems that I should avoid AC-coupling? From the AFE7950EVM, I see the following resistor network, but the resistor values seem low, would this affect the 100 ohm internal termination at the SYSREF inputs? No pull-ups needed? Please advise.

  • 0 in reply to Jack Zhang
    TI__Genius 12550 points

    Hi,

    I believe the above SYSREF circuits is not meant for LVDS output. 

    I could see the above circuit is for LCPECL output, where the resistive circuit in DC coupled mode is used to reduced the amplitude and no need to have additional DC biasing.

    LMK04832 / LMK04828 device already have various output formats with CM voltage and large swing and can be utilize for AFEs in DC coupled mode to avoid additional biasing circuits.

    Thanks!

    Regards,

    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Intellectual 480 points

    Apologies, I'm still a little confused. Is the recommended implementation for my application (LVDS output from LMK04832 to SYSREF input on AFE7950 as LVDS) not to have any sort of biasing circuit (no AC caps, which would block DC, and no pull-ups/downs)? That would be great, but just wanted to make sure, because the AFE79XX sch checklist states that SYSREF CM needs to be set to 0.6 V.

  • 0 in reply to Jack Zhang
    TI__Genius 12550 points

    Hi,

    Yes, you can go ahead with the above recommended resistive network and it can work for LVDS and LCPECL output format from LMK04832 to achieve 0.6V common mode voltage.

    Thanks!

    Regards,

    Ajeet Pal