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Original question:

LMK05028EVM: DPLL1 nor DPLL2 did not get lock

LMK05028EVM: DPLLs are not locked

user4779049
Expert 2155 points
Part Number: LMK05028EVM
Other Parts Discussed in Thread: LMK05028

Hi Team,

 

Question: Please let me know how to configure DPLx feedback divider registers properly  through TICS Pro GUI.

Following your advice, I tried the following procedure.

  1. Supply 5 V power to the EVM
  2. Apply 25 MHz, 0-2 V reference clock.
  3. Run TICS pro Version 1.7.5.0
  4. Click Select device => Network-- => LMK05028
  5. Click Default Configuration => EVM Default
  6. Moved to the main script page
  7. Click Update frequency plan
  8. Click RUN Script
  9. Click Write All registers
  10.  Click Soft Reset Chip
  11. Checked LEDs for Stats 1 and 2.

They were still light on.

LEDs for the hold over were on or off corresponding to the

presence and absence of the REF clock.

I concluded that DPLL1 nor DPLL2 did not get lock.

 

I checked register related to the PLLx feedback path

and found that they might be inappropriate values  as follows:

Please let me know how to set valid values for these registers.

 

DPLL1:  VCO freq.= 5000 MHz

Post Div = 4

Out Div for port 7 = 8

Out7 Freq. = 5000/4/8=156.25 as expected

 

On the feedback path

Pre-Div  R362 = 0x02 resulting 4

Feedback Div.   R363~R366=0x313 = 787

Num   R367~R371 = 0x80 00 00 00 00

DEN   R372~R376 = 0x00 00 00 00 00

Ignoring Num and DEN, the feedback frequency was 5000/4/4/787=0.397078 MHz.

 

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

DPLL2:  VCO freq.= 5529.6 MHz

Post Div = 5

Out Div for port 0 = 9

Out0 Freq. = 5529.6/5/9=122.88 as expected

 

On the feedback path

Pre-Div  R501 = 0x01 resulting 3

Feedback Div.   R502~R505=0x0e = 14

Num   R506~R510 = 0xbe df a4 3f 18

DEN   R511~R515 = 0xff ff ff fe ec

Ignoring Num and DEN, the feedback frequency was 5529.6/5/3/14=26.3314 MHz.

 

Please let me know how to configure these registers properly  through TICS Pro GUI.

Mita

  • 0
    TI__Expert 8585 points

    Hello Mita,

    Can you please provide me the TICS Pro configuration file? I will review it to determine the issue.

    Regards,

    Kia Rahbar

  • 0 in reply to Kia Rahbar
    Expert 2155 points

    Kis-san,

    Thank you for your prompt feedback.

    As I reported, I used EVM Default configuration

            4. Click Select device => Network-- => LMK05028

            5. Click Default Configuration => EVM Default

    Just in case, I attached the saved configuration file.

    LMK05028-default.tcs

    Mita

  • 0 in reply to user4779049
    TI__Expert 8585 points

    Hello Mita,

    The default configuration requires a TCXO input. Can you please confirm the onboard EVM TCXO is powered on? The DPLLs will not lock until the TCXO and XO inputs are validated. The TCXO and XO inputs will be validated when these flags are low.

    Can you also check that the appropriate reference is being validated? If a reference is valid, the REFxVALSTAT flag will be high.

    If the reference you are using is not valid, but the TCXO and XO inputs are valid, you will need to toggle (turn on/off) the frequency detect threshold and missing clock highlighted below.

    Sometimes when you perform a run script, you will need to reset the reference input monitors.

    Also, I would recommend following this procedure:

    1. Supply 5 V power to the EVM
    2. Apply 25 MHz, 0-2 V reference clock.
    3. Ensure the 48.0048 MHz onboard XO input is powered on (or is disabled and fed externally from a signal generator)
    4. Ensure the 10 MHz onboard TCXO input is powered on (or fed externally from a signal generator)
    5. Run TICS pro Version 1.7.5.0
    6. Click Select device => Network-- => LMK05028
    7. Click Default Configuration => EVM Default
    8. Click Write All registers
    9.  Click Soft Reset Chip
    10. Checked LEDs for Stats 1 and 2.

    I would recommend skipping the Click Update frequency plan and Click RUN Script steps if you are only evaluating the default configuration. The loaded configuration will have the appropriate settings and will not require these steps.

    Regards,

    Kia Rahbar

  • 0 in reply to Kia Rahbar
    Expert 2155 points

    Kia-san,

    Thank you for your feedback.

    I am confident that XO and TCXO were functioning.

    I also try the following steps.

    1. Supply 5 V power to the EVM     => I did 
    2. Apply 25 MHz, 0-2 V reference clock   => I did .
    3. Ensure the 48.0048 MHz onboard XO input is powered on (or is disabled and fed externally from a signal generator)    => I used on board XO
    4. Ensure the 10 MHz onboard TCXO input is powered on (or fed externally from a signal generator)  => I used on board TCXO
    5. Run TICS pro Version 1.7.5.0   => I run this version TICS PRO
    6. Click Select device => Network-- => LMK05028   => Yes I selected LMK05028
    7. Click Default Configuration => EVM Default   => Yes, I selected EVM default
    8. Click Write All registers    => Yes I did 
    9.  Click Soft Reset Chip   => Yes I did
    10. Checked LEDs for Stats 1 and 2.   => Yes I checked LEDs and confirmed they were lighting 

    In addition to above procedure I have checked the register values related to the DPLL1 and DPLL2.
    I suspect that they were not properly programed.
    Can you check the resister values  and give me comments on them

    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    DPLL1: VCO freq.= 5000 MHz
    Post Div = 4
    Out Div for port 7 = 8
    Out7 Freq. = 5000/4/8=156.25 as expected


    On the feedback path
    Pre-Div R362 = 0x02 resulting 4
    Feedback Div. R363~R366=0x313 = 787
    Num R367~R371 = 0x80 00 00 00 00
    DEN R372~R376 = 0x00 00 00 00 00
    Ignoring Num and DEN, the feedback frequency was 5000/4/4/787=0.397078 MHz.
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    DPLL2: VCO freq.= 5529.6 MHz
    Post Div = 5
    Out Div for port 0 = 9
    Out0 Freq. = 5529.6/5/9=122.88 as expected


    On the feedback path
    Pre-Div R501 = 0x01 resulting 3
    Feedback Div. R502~R505=0x0e = 14
    Num R506~R510 = 0xbe df a4 3f 18
    DEN R511~R515 = 0xff ff ff fe ec
    Ignoring Num and DEN, the feedback frequency was 5529.6/5/3/14=26.3314 MHz.

    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

    Mita

  • 0 in reply to user4779049
    TI__Expert 8585 points

    Hello Mita,

    The issue was the missing clock detector for the reference input. This was resulting in the reference not being detected by the device and therefore the DPLLs not locking.

    I have updated the missing clock detector setting to 1 as shown below and the device locks properly now.

    Please follow these steps and the DPLLs will lock properly:

    1. Supply 5 V power to the EVM
    2. Apply 25 MHz, 0-2 V reference clock.
    3. Ensure the 48.0048 MHz onboard XO input is powered on.
    4. Ensure the 10 MHz onboard TCXO input is powered on.
    5. Run TICS pro Version 1.7.5.0
    6. Click Select device => Network-- => LMK05028
    7. Click File => Load and then load this configuration:

    LMK05028-default_working.tcs

    1. Click Write All registers 
    2. Click Soft Reset Chip
    3. Checked LEDs for Stats 1 and 2. Might take 5 to 10 seconds for them to show that the DPLL is locked.

    Regards,

    Kia Rahbar

  • 0 in reply to Kia Rahbar
    Expert 2155 points

    Kia-san,

    Thank you for you advise.

    I will try it some day in next week.

    BTW: Can you check the validity of the  feedback divider registers, I listed, and give me your comment?

    Mita 

  • +1 in reply to user4779049
    TI__Expert 8585 points

    Hello Mita,

    The feedback divider settings are appropriate.

    Below I will be using the following equation to show that the feedback divider settings are appropriate for the 25 MHz reference and each DPLLs VCO frequency.

    DPLL1:

    1. VCO = (fINx / RINx) × P1PLL × PRREF × (INTREF + NUMREF/ DENREF)
      1. fINx = 25 MHz
      2. RINx = 63
      3. P1PLL = 4
      4. PRREF = 4
      5. INTREF = 787
      6. NUMREF = 549755813888
      7. DENREF = 2^40 = 1099511627776
    2. VCO = (25e6/ 63) × 4× 4× (787+ 549755813888/ 1099511627776)
    3. VCO = 5000 MHz

    Please note you can find the DPLL1 feedback settings here.

    DPLL2:

    1. VCO = (fINx / RINx) × P1PLL × PRREF × (INTREF + NUMREF/ DENREF)
      1. fINx = 25 MHz
      2. RINx = 1
      3. P1PLL = 5
      4. PRREF = 3
      5. INTREF = 14
      6. NUMREF = 819795869464
      7. DENREF = 1099511627500
    2. VCO = (25e6/ 1) × 5 × 3 × (14+ 819795869464/ 1099511627500)
    3. VCO = 5529.6 MHz

    Please note you can find the DPLL2 feedback settings here.

    As you can see the feedback divider settings are correct. Typically DPLL locking issues are due to the reference validation settings, not the feedback divider.

    Regards,

    Kia Rahbar

  • 0 in reply to Kia Rahbar
    Expert 2155 points

    Kia-san,

    Thank you for your answers.

    I understand them.

    Mita