LMK04828BEVM: LMK04828B Spurious level simulation

Hi Kavya,

Such a capability is not included with LMK04828 because the only paths for spurious injection are crosstalk-related, where magnitude changes are difficult to predict depending on which outputs have been chosen, the supply filtering network, the PCB layout, use of switching supplies, etc. This is as compared to LMX devices where the behavior of the fractional divider is directly calculable and highly predictable.

Instead, here's some general notes on expectations for spurious of LMK04828:

• Spurs below the loop bandwidth, which do not change with changes to PLL behavior, are injected on either the reference path or the input power supply path. For spurs below PLL1 bandwidth (if used), the relevant inputs are CLKinX and the relevant supply is VCC_PLL1 for CLKin0/1 or VCC_OSCout for CLKin2; for spurs below PLL2 bandwidth but above PLL1 bandwidth (if used), or for spurs below PLL2 bandwidth when only PLL2 is used, the relevant input is the VCXO or the reference on OSCin, and the relevant supplies are VCC_OSCin and the supply on the VCXO if used.
• Spurs below the loop bandwidth but which do change with changes to PLL loop bandwidth may be injected on the VCC_VCO, VCC_PLL1, or VCC_CP supplies. They could also be coupled into the loop filter and could be modulating the tuning voltage for the VCO.
• Spurs at higher offsets tend to be crosstalk spurs from the interaction of nearby outputs at dissimilar frequencies. Note in the pinout diagram of the datasheet that certain outputs belong to clock groups, which share a power supply. If the dividers in these clock groups are running at dissimilar frequencies, there is no mechanism to filter power supply crosstalk between the two dividers in the same clock group, and so an f1 % f2 spur will be present. Likewise, if the SYSREF outputs are continuously active, this can couple a Dclk % SYSREF spur onto the outputs (hence the ability to use "pulsed" SYSREF, and the SYSREF_REQ feature, which allow use of the SYSREF divider without generating substantial crosstalk). Outputs at different frequencies on separate clock groups may still crosstalk to each other, but the crosstalk should be reduced, especially if a ferrite bead with reasonably high impedance at the device clock frequencies is present in the clock group supply paths. And of course, if outputs with dissimilar frequencies are routed next to or on top of each other, this can lead to capacitive or inductive coupling between the outputs, which will show up as crosstalk.

Remediation strategies include proper frequency planning to keep dissimilar output frequencies on separate clock groups, using pulsed or requested SYSREF instead of continuous SYSREF, ensuring a spur-free reference, and keeping power supplies separated and filtered when they operate with different continuous frequency content.

Regards,

Derek Payne