Hi team:
I would like to confirm whether we have a low consumption device as <1W to substitute the LMK05318B.
tks for you confirmation.
Hello Allen,
Here is a presentation that shows you how to use the LMK05318B GUI:
LMK05318B TICS Pro GUI Overview.pdf
The following link shows all of our clock jitter cleaners & synchronizers: TI clock jitter cleaners & synchronizers
All of the devices will likely have > 1W power consumption.
To get below 1 W, you will need to use less outputs, a single PLL, and low current drawing output format (such as LVDS).
For example, Section 11.2 in the data sheet provides the equations for calculating the approximate power consumption for the LMK05318B.
Using the equations above and configuring the device to use APLL1 only, OUT0/OUT1 only, and LVDS output format, the power will be as follows.
We have:
As you can see, even with using 2 outputs and a single PLL, this device will still be above 1 W power consumption.
The same situation will occur with all of our other network synchronizers (LMK5B12204, LMK05028, LMK5B33216, LMK5C33216).
Therefore, if you need a device with DPLLs (network synchronizer), you will most likely have above 1 W power consumption.
Our jitter cleaners (LMK04000, LMK04001, LMK04002, LMK04010, LMK04011, LMK04031, LMK04033) will also have a power consumption above 1W.
These jitter cleaners have a current consumption as shown below:
If we take the smallest value of 335 mA, we still get a power consumption equal to 1.1055 W (335 mA * 3.3 V).
The reason our jitter cleaner & network synchronizer devices will rarely have below 1 W power consumption is because they have a 3.3 V supply.
The LMK04610 would be your best and only option (other than the CDCE813-Q1 which has 3 outputs).
The LMK04610 would have a consumption as shown below:
Regards,
Kia Rahbar
Hello Allen,
To disable APLL1 and use APLL2 only, you must perform the following:
1. Disable APLL1 on the APLL1 page as shown below.
2. Enable APLL2 and set PLL2 Reference Select to "XO". If PLL2 Reference Select is set to "VCO1- cascaded Mode (default)", you will not get output clocks from APLL2 because its reference is APLL1 and APLL1 has been disabled.
I strongly recommend against doing this for the following reasons:
1. If you use APLL2 only, you will not be able to use the DPLL.
2. If you use APLL2 only, your output clocks phase noise performance will be worse than using APLL1.
3. The current consumption is actually greater when using APLL2 instead of APLL1 and the DPLL. As you can see in the image below APLL2 uses 120 mA of current when enabled. APLL1 and the DPLL use 110 mA of current when enabled. When disabled APLL2 use 20 mA of current. When disabled APLL1 and the DPLL will still consume 20 mA (this is not specified in the data sheet, but I have verified in our lab).
The only case where I would recommend using APLL2 only is if all of your output frequencies are not an integer division of the 2.5 GHz BAW VCO of APLL1. In this case it is not mathematically possible to use APLL1, so you would have to default to APLL2 only.
If your frequencies are an integer division of the 2.5 GHz BAW VCO, then I strongly recommend using APLL1 only.
Regards,
Kia Rahbar
Hi Kia:
many tks with your detail explanation. I would like to double confirm with you about the BAW frequency lock detect setting as the attached file.
The customer feedback that if they disable this setting, the end equipment of Opto Module will become more unstable.
but if enable this setting, the Opto module will become more stable.
but base on this description in the SW， it is conflict between the DPLL(customer need to enable) and BAW frequency lock detect performance.
would you help to check this timing config-file and B/D in this case? tks!
