Other Parts Discussed in Thread: LMK04828, TIDA-01024,
I checked some documents for JESD204B clocking and they recommend all devclk and sysref should be length match.
My application is similar to TIDA-01024. Two LMK04828 are connected as daisy cain and supply devclk and sysref to FPGAs and multiple PLLs.
PLL produces devclk_dac and sysref_dac for a DAC.
From LMK04828 to FPGA, there are devlck_fpga and sysref_fpga.
From LMK04828 to PLL, there are devlck, sysrefreq and sync.
From PLL to DAc, there are devclk_dac, sysref_dac
Length match on is mentioned only for DCLKout12 and SDCLKout13 of first LMK for daisy chain on TIDA-01024 user guide.
How about other signals devclk_fpga, sysref_fpga, devclk, sysrefreq, sync, devclk_dac and sysref_dac?
All devclk_dac and sysref_dac signals from PLLs to DACs will be routed as same length.
1> Are devclk_fpga and sysref_fpga should be length matched with devclk, sysrefreq and sync?
Even though devclk_fpga and sysref_fpga are matched length with devclk, sysrefreq and sync, I am not sure if phase of sysref_dac and sysref_fpga will be aligned.
2> Which case is better for sysref_dac.
One is that LMK produces sysref_dac or the other s that PLL produces sysref_dac by sysrefreq from LMK?